mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-10-31 00:01:35 +00:00
6ab3d5624e
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
177 lines
3.5 KiB
ArmAsm
177 lines
3.5 KiB
ArmAsm
/*
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* linux/arch/m32r/boot/compressed/head.S
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*
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* Copyright (c) 2001-2003 Hiroyuki Kondo, Hirokazu Takata,
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* Hitoshi Yamamoto, Takeo Takahashi
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* Copyright (c) 2004 Hirokazu Takata
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*/
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.text
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#include <linux/linkage.h>
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#include <asm/addrspace.h>
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#include <asm/page.h>
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#include <asm/assembler.h>
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/*
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* This code can be loaded anywhere, as long as output will not
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* overlap it.
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*
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* NOTE: This head.S should *NOT* be compiled with -fpic.
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*
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*/
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.global startup
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.global __bss_start, _ebss, end, zimage_data, zimage_len
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__ALIGN
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startup:
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ldi r0, #0x0000 /* SPI, disable EI */
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mvtc r0, psw
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ldi r12, #-8
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bl 1f
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.fillinsn
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1:
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seth r1, #high(CONFIG_MEMORY_START + 0x00400000) /* Start address */
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add r12, r14 /* Real address */
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sub r12, r1 /* difference */
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.global got_len
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seth r3, #high(_GLOBAL_OFFSET_TABLE_+8)
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or3 r3, r3, #low(_GLOBAL_OFFSET_TABLE_+12)
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add r3, r14
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/* Update the contents of global offset table */
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ldi r1, #low(got_len)
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srli r1, #2
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beqz r1, 2f
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.fillinsn
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1:
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ld r2, @r3
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add r2, r12
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st r2, @r3
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addi r3, #4
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addi r1, #-1
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bnez r1, 1b
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.fillinsn
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2:
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/* XXX: resolve plt */
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/*
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* Clear BSS first so that there are no surprises...
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*/
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#ifdef CONFIG_ISA_DUAL_ISSUE
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seth r2, #high(__bss_start)
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or3 r2, r2, #low(__bss_start)
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add r2, r12
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seth r3, #high(_ebss)
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or3 r3, r3, #low(_ebss)
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add r3, r12
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sub r3, r2
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; R4 = BSS size in longwords (rounded down)
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mv r4, r3 || ldi r1, #0
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srli r4, #4 || addi r2, #-4
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beqz r4, .Lendloop1
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.Lloop1:
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#ifndef CONFIG_CHIP_M32310
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; Touch memory for the no-write-allocating cache.
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ld r0, @(4,r2)
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#endif
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st r1, @+r2 || addi r4, #-1
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st r1, @+r2
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st r1, @+r2
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st r1, @+r2 || cmpeq r1, r4 ; R4 = 0?
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bnc .Lloop1
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.Lendloop1:
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and3 r4, r3, #15
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addi r2, #4
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beqz r4, .Lendloop2
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.Lloop2:
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stb r1, @r2 || addi r4, #-1
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addi r2, #1
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bnez r4, .Lloop2
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.Lendloop2:
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#else /* not CONFIG_ISA_DUAL_ISSUE */
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seth r2, #high(__bss_start)
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or3 r2, r2, #low(__bss_start)
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add r2, r12
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seth r3, #high(_ebss)
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or3 r3, r3, #low(_ebss)
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add r3, r12
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sub r3, r2
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mv r4, r3
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srli r4, #2 ; R4 = BSS size in longwords (rounded down)
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ldi r1, #0 ; clear R1 for longwords store
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addi r2, #-4 ; account for pre-inc store
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beqz r4, .Lendloop1 ; any more to go?
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.Lloop1:
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st r1, @+r2 ; yep, zero out another longword
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addi r4, #-1 ; decrement count
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bnez r4, .Lloop1 ; go do some more
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.Lendloop1:
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#endif /* not CONFIG_ISA_DUAL_ISSUE */
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seth r1, #high(end)
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or3 r1, r1, #low(end)
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add r1, r12
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mv sp, r1
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/*
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* decompress the kernel
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*/
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mv r0, sp
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srli r0, 31 /* MMU is ON or OFF */
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seth r1, #high(zimage_data)
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or3 r1, r1, #low(zimage_data)
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add r1, r12
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seth r2, #high(zimage_len)
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or3 r2, r2, #low(zimage_len)
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mv r3, sp
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bl decompress_kernel
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#if defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_OPSP) || defined(CONFIG_CHIP_VDEC2)
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/* Cache flush */
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ldi r0, -1
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ldi r1, 0xd0 ; invalidate i-cache, copy back d-cache
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stb r1, @r0
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#elif defined(CONFIG_CHIP_M32102)
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/* Cache flush */
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ldi r0, -2
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ldi r1, 0x0100 ; invalidate
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stb r1, @r0
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#elif defined(CONFIG_CHIP_M32104)
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/* Cache flush */
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ldi r0, -2
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ldi r1, 0x0700 ; invalidate i-cache, copy back d-cache
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sth r1, @r0
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#else
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#error "put your cache flush function, please"
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#endif
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mv r0, sp
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srli r0, 31 /* MMU is ON or OFF */
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slli r0, 31
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or3 r0, r0, #0x2000
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seth r1, #high(CONFIG_MEMORY_START)
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or r0, r1
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jmp r0
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.balign 512
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fake_headers_as_bzImage:
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.short 0
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.ascii "HdrS"
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.short 0x0202
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.short 0
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.short 0
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.byte 0x00, 0x10
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.short 0
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.byte 0
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.byte 1
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.byte 0x00, 0x80
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.long 0
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.long 0
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