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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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a8d902db22
Hardcoded MMIO base addresses are used a few places throughout the platform code. Move these into the chip-specific header file so that adding support for new chips becomes a bit easier. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
113 lines
3.0 KiB
C
113 lines
3.0 KiB
C
/*
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* Register definitions for the Power Manager (PM)
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*/
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#ifndef __ARCH_AVR32_MACH_AT32AP_PM_H__
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#define __ARCH_AVR32_MACH_AT32AP_PM_H__
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/* PM register offsets */
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#define PM_MCCTRL 0x0000
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#define PM_CKSEL 0x0004
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#define PM_CPU_MASK 0x0008
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#define PM_HSB_MASK 0x000c
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#define PM_PBA_MASK 0x0010
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#define PM_PBB_MASK 0x0014
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#define PM_PLL0 0x0020
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#define PM_PLL1 0x0024
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#define PM_IER 0x0040
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#define PM_IDR 0x0044
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#define PM_IMR 0x0048
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#define PM_ISR 0x004c
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#define PM_ICR 0x0050
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#define PM_GCCTRL(x) (0x0060 + 4 * (x))
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#define PM_RCAUSE 0x00c0
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/* Bitfields in CKSEL */
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#define PM_CPUSEL_OFFSET 0
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#define PM_CPUSEL_SIZE 3
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#define PM_CPUDIV_OFFSET 7
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#define PM_CPUDIV_SIZE 1
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#define PM_HSBSEL_OFFSET 8
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#define PM_HSBSEL_SIZE 3
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#define PM_HSBDIV_OFFSET 15
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#define PM_HSBDIV_SIZE 1
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#define PM_PBASEL_OFFSET 16
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#define PM_PBASEL_SIZE 3
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#define PM_PBADIV_OFFSET 23
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#define PM_PBADIV_SIZE 1
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#define PM_PBBSEL_OFFSET 24
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#define PM_PBBSEL_SIZE 3
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#define PM_PBBDIV_OFFSET 31
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#define PM_PBBDIV_SIZE 1
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/* Bitfields in PLL0 */
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#define PM_PLLEN_OFFSET 0
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#define PM_PLLEN_SIZE 1
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#define PM_PLLOSC_OFFSET 1
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#define PM_PLLOSC_SIZE 1
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#define PM_PLLOPT_OFFSET 2
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#define PM_PLLOPT_SIZE 3
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#define PM_PLLDIV_OFFSET 8
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#define PM_PLLDIV_SIZE 8
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#define PM_PLLMUL_OFFSET 16
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#define PM_PLLMUL_SIZE 8
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#define PM_PLLCOUNT_OFFSET 24
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#define PM_PLLCOUNT_SIZE 6
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#define PM_PLLTEST_OFFSET 31
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#define PM_PLLTEST_SIZE 1
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/* Bitfields in ICR */
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#define PM_LOCK0_OFFSET 0
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#define PM_LOCK0_SIZE 1
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#define PM_LOCK1_OFFSET 1
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#define PM_LOCK1_SIZE 1
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#define PM_WAKE_OFFSET 2
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#define PM_WAKE_SIZE 1
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#define PM_CKRDY_OFFSET 5
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#define PM_CKRDY_SIZE 1
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#define PM_MSKRDY_OFFSET 6
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#define PM_MSKRDY_SIZE 1
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/* Bitfields in GCCTRL0 */
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#define PM_OSCSEL_OFFSET 0
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#define PM_OSCSEL_SIZE 1
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#define PM_PLLSEL_OFFSET 1
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#define PM_PLLSEL_SIZE 1
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#define PM_CEN_OFFSET 2
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#define PM_CEN_SIZE 1
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#define PM_DIVEN_OFFSET 4
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#define PM_DIVEN_SIZE 1
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#define PM_DIV_OFFSET 8
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#define PM_DIV_SIZE 8
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/* Bitfields in RCAUSE */
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#define PM_POR_OFFSET 0
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#define PM_POR_SIZE 1
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#define PM_EXT_OFFSET 2
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#define PM_EXT_SIZE 1
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#define PM_WDT_OFFSET 3
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#define PM_WDT_SIZE 1
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#define PM_NTAE_OFFSET 4
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#define PM_NTAE_SIZE 1
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/* Bit manipulation macros */
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#define PM_BIT(name) \
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(1 << PM_##name##_OFFSET)
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#define PM_BF(name,value) \
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(((value) & ((1 << PM_##name##_SIZE) - 1)) \
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<< PM_##name##_OFFSET)
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#define PM_BFEXT(name,value) \
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(((value) >> PM_##name##_OFFSET) \
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& ((1 << PM_##name##_SIZE) - 1))
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#define PM_BFINS(name,value,old)\
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(((old) & ~(((1 << PM_##name##_SIZE) - 1) \
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<< PM_##name##_OFFSET)) \
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| PM_BF(name,value))
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/* Register access macros */
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#define pm_readl(reg) \
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__raw_readl((void __iomem __force *)PM_BASE + PM_##reg)
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#define pm_writel(reg,value) \
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__raw_writel((value), (void __iomem __force *)PM_BASE + PM_##reg)
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#endif /* __ARCH_AVR32_MACH_AT32AP_PM_H__ */
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