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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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d04a0f79f5
The extended mode TLB requires both 64-bit PTEs and a 64-bit pgprot, correspondingly, the PGD also has to be 64-bits, so fix that up. The kernel and user permission bits really are decoupled in early cuts of the silicon, which means that we also have to set corresponding kernel permissions on user pages or we end up with user pages that the kernel simply can't touch (!). Finally, with those things corrected, really enable MMUCR.ME and correct the PTEA value (this simply needs to be the upper 32-bits of the PTE, with the size and protection bit encoding). Signed-off-by: Paul Mundt <lethal@linux-sh.org>
56 lines
1.4 KiB
C
56 lines
1.4 KiB
C
/*
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* include/asm-sh/cpu-sh4/mmu_context.h
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*
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* Copyright (C) 1999 Niibe Yutaka
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_CPU_SH4_MMU_CONTEXT_H
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#define __ASM_CPU_SH4_MMU_CONTEXT_H
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#define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */
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#define MMU_PTEL 0xFF000004 /* Page table entry register LOW */
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#define MMU_TTB 0xFF000008 /* Translation table base register */
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#define MMU_TEA 0xFF00000C /* TLB Exception Address */
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#define MMU_PTEA 0xFF000034 /* Page table entry assistance register */
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#define MMUCR 0xFF000010 /* MMU Control Register */
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#define MMU_ITLB_ADDRESS_ARRAY 0xF2000000
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#define MMU_UTLB_ADDRESS_ARRAY 0xF6000000
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#define MMU_PAGE_ASSOC_BIT 0x80
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#ifdef CONFIG_X2TLB
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#define MMUCR_ME (1 << 7)
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#else
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#define MMUCR_ME (0)
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#endif
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#ifdef CONFIG_SH_STORE_QUEUES
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#define MMUCR_SQMD (1 << 9)
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#else
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#define MMUCR_SQMD (0)
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#endif
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#define MMU_NTLB_ENTRIES 64
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#define MMU_CONTROL_INIT (0x05|MMUCR_SQMD|MMUCR_ME)
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#define MMU_ITLB_DATA_ARRAY 0xF3000000
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#define MMU_UTLB_DATA_ARRAY 0xF7000000
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#define MMU_UTLB_ENTRIES 64
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#define MMU_U_ENTRY_SHIFT 8
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#define MMU_UTLB_VALID 0x100
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#define MMU_ITLB_ENTRIES 4
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#define MMU_I_ENTRY_SHIFT 8
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#define MMU_ITLB_VALID 0x100
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#define TRA 0xff000020
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#define EXPEVT 0xff000024
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#define INTEVT 0xff000028
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#endif /* __ASM_CPU_SH4_MMU_CONTEXT_H */
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