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611e385087
The ptrace-gpr test includes some inline asm to load GPR and FPR registers. It then goes back to C to wait for the parent to trace it and then checks register contents. The split between inline asm and C is fragile, it relies on the compiler not using any non-volatile GPRs after the inline asm block. It also requires a very large and unwieldy inline asm block. So convert the logic to set registers, wait, and store registers to a single asm function, meaning there's no window for the compiler to intervene. Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20220627140239.2464900-10-mpe@ellerman.id.au
53 lines
1.3 KiB
ArmAsm
53 lines
1.3 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* test helper assembly functions
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*
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* Copyright (C) 2016 Simon Guo, IBM Corporation.
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* Copyright 2022 Michael Ellerman, IBM Corporation.
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*/
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#include "basic_asm.h"
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#define GPR_SIZE __SIZEOF_LONG__
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#define FIRST_GPR 14
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#define NUM_GPRS (32 - FIRST_GPR)
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#define STACK_SIZE (NUM_GPRS * GPR_SIZE)
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// gpr_child_loop(int *read_flag, int *write_flag,
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// unsigned long *gpr_buf, double *fpr_buf);
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FUNC_START(gpr_child_loop)
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// r3 = read_flag
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// r4 = write_flag
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// r5 = gpr_buf
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// r6 = fpr_buf
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PUSH_BASIC_STACK(STACK_SIZE)
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// Save non-volatile GPRs
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OP_REGS PPC_STL, GPR_SIZE, FIRST_GPR, 31, %r1, STACK_FRAME_LOCAL(0, 0), FIRST_GPR
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// Load GPRs with expected values
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OP_REGS PPC_LL, GPR_SIZE, FIRST_GPR, 31, r5, 0, FIRST_GPR
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// Load FPRs with expected values
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OP_REGS lfd, 8, 0, 31, r6
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// Signal to parent that we're ready
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li r0, 1
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stw r0, 0(r4)
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// Wait for parent to finish
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1: lwz r0, 0(r3)
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cmpwi r0, 0
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beq 1b // Loop while flag is zero
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// Save GPRs back to caller buffer
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OP_REGS PPC_STL, GPR_SIZE, FIRST_GPR, 31, r5, 0, FIRST_GPR
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// Save FPRs
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OP_REGS stfd, 8, 0, 31, r6
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// Reload non-volatile GPRs
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OP_REGS PPC_LL, GPR_SIZE, FIRST_GPR, 31, %r1, STACK_FRAME_LOCAL(0, 0), FIRST_GPR
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POP_BASIC_STACK(STACK_SIZE)
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