mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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b8b16293ce
Update event topics, metrics to be generated from the TMA spreadsheet and other small clean ups. Signed-off-by: Ian Rogers <irogers@google.com> Tested-by: Thomas Falcon <thomas.falcon@intel.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Andreas Färber <afaerber@suse.de> Cc: Caleb Biggers <caleb.biggers@intel.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Perry Taylor <perry.taylor@intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Weilin Wang <weilin.wang@intel.com> Link: https://lore.kernel.org/r/20250328175006.43110-31-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
56 lines
2.6 KiB
JSON
56 lines
2.6 KiB
JSON
[
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{
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"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
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"Counter": "0,1,2,3",
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"EventCode": "0x28",
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"EventName": "CORE_POWER.LVL0_TURBO_LICENSE",
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"PublicDescription": "Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",
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"SampleAfterValue": "200003",
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"UMask": "0x7"
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},
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{
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"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",
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"Counter": "0,1,2,3",
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"EventCode": "0x28",
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"EventName": "CORE_POWER.LVL1_TURBO_LICENSE",
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"PublicDescription": "Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",
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"SampleAfterValue": "200003",
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"UMask": "0x18"
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},
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{
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"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
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"Counter": "0,1,2,3",
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"EventCode": "0x28",
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"EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
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"PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchitecture). This includes high current AVX 512-bit instructions.",
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"SampleAfterValue": "200003",
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"UMask": "0x20"
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},
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{
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"BriefDescription": "Core cycles the core was throttled due to a pending power level request.",
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"Counter": "0,1,2,3",
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"EventCode": "0x28",
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"EventName": "CORE_POWER.THROTTLE",
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"PublicDescription": "Core cycles the out-of-order engine was throttled due to a pending power level request.",
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"SampleAfterValue": "200003",
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"UMask": "0x40"
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},
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{
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"BriefDescription": "Number of hardware interrupts received by the processor.",
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"Counter": "0,1,2,3",
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"EventCode": "0xCB",
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"EventName": "HW_INTERRUPTS.RECEIVED",
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"PublicDescription": "Counts the number of hardware interruptions received by the processor.",
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"SampleAfterValue": "203",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
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"Counter": "0,1,2,3",
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"EventCode": "0x09",
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"EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
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"SampleAfterValue": "2000003",
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"UMask": "0x1"
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}
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]
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