mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-01 23:46:45 +00:00
1f9e24e4df
Bring in the events at v1.00:
d90a6737d0
Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Link: https://lore.kernel.org/r/20250630163101.1920170-12-irogers@google.com
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
216 lines
11 KiB
JSON
216 lines
11 KiB
JSON
[
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{
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"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles.",
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"Counter": "2,3,4,5,6,7,8,9",
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"Data_LA": "1",
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"EventCode": "0xcd",
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"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x400",
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"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
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"SampleAfterValue": "53",
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"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
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"Counter": "2,3,4,5,6,7,8,9",
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"Data_LA": "1",
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"EventCode": "0xcd",
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"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x80",
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"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
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"SampleAfterValue": "1009",
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"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
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"Counter": "2,3,4,5,6,7,8,9",
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"Data_LA": "1",
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"EventCode": "0xcd",
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"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x10",
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"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
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"SampleAfterValue": "20011",
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"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles.",
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"Counter": "2,3,4,5,6,7,8,9",
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"Data_LA": "1",
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"EventCode": "0xcd",
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"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_2048",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x800",
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"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
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"SampleAfterValue": "23",
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"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
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"Counter": "2,3,4,5,6,7,8,9",
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"Data_LA": "1",
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"EventCode": "0xcd",
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"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x100",
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"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
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"SampleAfterValue": "503",
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"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
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"Counter": "2,3,4,5,6,7,8,9",
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"Data_LA": "1",
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"EventCode": "0xcd",
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"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x20",
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"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
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"SampleAfterValue": "100007",
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"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
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"Counter": "2,3,4,5,6,7,8,9",
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"Data_LA": "1",
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"EventCode": "0xcd",
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"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x4",
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"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
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"SampleAfterValue": "100003",
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"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
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"Counter": "2,3,4,5,6,7,8,9",
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"Data_LA": "1",
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"EventCode": "0xcd",
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"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x200",
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"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
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"SampleAfterValue": "101",
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"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
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"Counter": "2,3,4,5,6,7,8,9",
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"Data_LA": "1",
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"EventCode": "0xcd",
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"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x40",
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"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
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"SampleAfterValue": "2003",
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"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
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"Counter": "2,3,4,5,6,7,8,9",
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"Data_LA": "1",
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"EventCode": "0xcd",
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"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x8",
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"PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency. Available PDIST counters: 0",
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"SampleAfterValue": "50021",
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"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Retired memory store access operations. A PDist event for PEBS Store Latency Facility.",
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"Counter": "0,1",
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"Data_LA": "1",
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"EventCode": "0xcd",
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"EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE",
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"PublicDescription": "Counts Retired memory accesses with at least 1 store operation. This PEBS event is the precisely-distributed (PDist) trigger covering all stores uops for sampling by the PEBS Store Latency Facility. The facility is described in Intel SDM Volume 3 section 19.9.8 Available PDIST counters: 0",
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"SampleAfterValue": "1000003",
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"UMask": "0x2",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts demand data reads that were supplied by DRAM.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xB7",
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"EventName": "OCR.DEMAND_DATA_RD.DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x7BC000001",
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"PublicDescription": "Counts demand data reads that were supplied by DRAM. Available PDIST counters: 0",
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"SampleAfterValue": "100003",
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"UMask": "0x1",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts demand data reads that were supplied by DRAM.",
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"Counter": "0,1,2,3",
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"EventCode": "0x2A,0x2B",
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"EventName": "OCR.DEMAND_DATA_RD.DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x1E780000001",
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"PublicDescription": "Counts demand data reads that were supplied by DRAM. Available PDIST counters: 0",
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"SampleAfterValue": "100003",
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"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xB7",
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"EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x13FBFC00001",
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"PublicDescription": "Counts demand data reads that were not supplied by the L3 cache. Available PDIST counters: 0",
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"SampleAfterValue": "100003",
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"UMask": "0x1",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
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"Counter": "0,1,2,3",
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"EventCode": "0x2A,0x2B",
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"EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x9E7FA000001",
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"PublicDescription": "Counts demand data reads that were not supplied by the L3 cache. Available PDIST counters: 0",
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"SampleAfterValue": "100003",
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"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xB7",
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"EventName": "OCR.DEMAND_RFO.L3_MISS",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x13FBFC00002",
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"PublicDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. Available PDIST counters: 0",
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"SampleAfterValue": "100003",
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"UMask": "0x1",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
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"Counter": "0,1,2,3",
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"EventCode": "0x2A,0x2B",
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"EventName": "OCR.DEMAND_RFO.L3_MISS",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x9E7FA000002",
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"PublicDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. Available PDIST counters: 0",
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"SampleAfterValue": "100003",
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"UMask": "0x1",
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"Unit": "cpu_core"
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}
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]
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