mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-01 23:46:45 +00:00
1f9e24e4df
Bring in the events at v1.00:
d90a6737d0
Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Link: https://lore.kernel.org/r/20250630163101.1920170-12-irogers@google.com
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
279 lines
12 KiB
JSON
279 lines
12 KiB
JSON
[
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{
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"BriefDescription": "Counts the number of L2 cache accesses from front door requests for Code Read, Data Read, RFO, ITOM, and L2 Prefetches. Does not include rejects or recycles, per core event.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0x24",
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"EventName": "L2_REQUEST.ALL",
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"SampleAfterValue": "1000003",
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"UMask": "0x1ff",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "L2 code requests",
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"Counter": "0,1,2,3,4,5,6,7,8,9",
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"EventCode": "0x24",
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"EventName": "L2_RQSTS.ALL_CODE_RD",
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"PublicDescription": "Counts the total number of L2 code requests.",
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"SampleAfterValue": "200003",
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"UMask": "0xe4",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Demand Data Read access L2 cache",
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"Counter": "0,1,2,3,4,5,6,7,8,9",
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"EventCode": "0x24",
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"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
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"PublicDescription": "Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once.",
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"SampleAfterValue": "200003",
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"UMask": "0xe1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0x2e",
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"EventName": "LONGEST_LAT_CACHE.MISS",
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"PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
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"SampleAfterValue": "1000003",
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"UMask": "0x41",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)",
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"Counter": "0,1,2,3,4,5,6,7,8,9",
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"EventCode": "0x2e",
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"EventName": "LONGEST_LAT_CACHE.MISS",
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"PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
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"SampleAfterValue": "100003",
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"UMask": "0x41",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0x2e",
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"EventName": "LONGEST_LAT_CACHE.REFERENCE",
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"PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
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"SampleAfterValue": "1000003",
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"UMask": "0x4f",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)",
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"Counter": "0,1,2,3,4,5,6,7,8,9",
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"EventCode": "0x2e",
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"EventName": "LONGEST_LAT_CACHE.REFERENCE",
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"PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
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"SampleAfterValue": "100003",
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"UMask": "0x4f",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts all retired load instructions.",
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"Counter": "0,1,2,3",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_INST_RETIRED.ALL_LOADS",
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"PublicDescription": "Counts Instructions with at least one architecturally visible load retired. Available PDIST counters: 0",
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"SampleAfterValue": "1000003",
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"UMask": "0x81",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Retired store instructions.",
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"Counter": "0,1,2,3",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_INST_RETIRED.ALL_STORES",
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"PublicDescription": "Counts all retired store instructions. Available PDIST counters: 0",
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"SampleAfterValue": "1000003",
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"UMask": "0x82",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts the number of load ops retired.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
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"SampleAfterValue": "1000003",
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"UMask": "0x81",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of store ops retired.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
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"SampleAfterValue": "1000003",
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"UMask": "0x82",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"Counter": "0,1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x400",
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"SampleAfterValue": "1000003",
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"UMask": "0x5",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"Counter": "0,1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x80",
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"SampleAfterValue": "1000003",
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"UMask": "0x5",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"Counter": "0,1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x10",
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"SampleAfterValue": "1000003",
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"UMask": "0x5",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"Counter": "0,1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x800",
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"SampleAfterValue": "1000003",
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"UMask": "0x5",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"Counter": "0,1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x100",
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"SampleAfterValue": "1000003",
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"UMask": "0x5",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"Counter": "0,1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x20",
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"SampleAfterValue": "1000003",
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"UMask": "0x5",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"Counter": "0,1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x4",
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"SampleAfterValue": "1000003",
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"UMask": "0x5",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"Counter": "0,1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x200",
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"SampleAfterValue": "1000003",
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"UMask": "0x5",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"Counter": "0,1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x40",
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"SampleAfterValue": "1000003",
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"UMask": "0x5",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
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"Counter": "0,1",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",
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"MSRIndex": "0x3F6",
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"MSRValue": "0x8",
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"SampleAfterValue": "1000003",
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"UMask": "0x5",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xd0",
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"EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",
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"SampleAfterValue": "1000003",
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"UMask": "0x6",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts demand data reads that have any type of response.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xB7",
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"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x10001",
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"PublicDescription": "Counts demand data reads that have any type of response. Available PDIST counters: 0",
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"SampleAfterValue": "100003",
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"UMask": "0x1",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts demand data reads that have any type of response.",
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"Counter": "0,1,2,3",
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"EventCode": "0x2A,0x2B",
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"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x10001",
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"PublicDescription": "Counts demand data reads that have any type of response. Available PDIST counters: 0",
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"SampleAfterValue": "100003",
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"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xB7",
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"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x10002",
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"PublicDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response. Available PDIST counters: 0",
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"SampleAfterValue": "100003",
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"UMask": "0x1",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
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"Counter": "0,1,2,3",
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"EventCode": "0x2A,0x2B",
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"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x10002",
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"PublicDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response. Available PDIST counters: 0",
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"SampleAfterValue": "100003",
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"UMask": "0x1",
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"Unit": "cpu_core"
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}
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]
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