mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-01 23:46:45 +00:00
bce986466f
Update event topic moving other topic events to cache and virtual memory. Signed-off-by: Ian Rogers <irogers@google.com> Tested-by: Thomas Falcon <thomas.falcon@intel.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Andreas Färber <afaerber@suse.de> Cc: Caleb Biggers <caleb.biggers@intel.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Perry Taylor <perry.taylor@intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Weilin Wang <weilin.wang@intel.com> Link: https://lore.kernel.org/r/20250328175006.43110-25-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
118 lines
3.3 KiB
JSON
118 lines
3.3 KiB
JSON
[
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{
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"BriefDescription": "DTLB load misses",
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"Counter": "0,1,2,3",
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"EventCode": "0x8",
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"EventName": "DTLB_LOAD_MISSES.ANY",
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"SampleAfterValue": "200000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "DTLB load miss caused by low part of address",
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"Counter": "0,1,2,3",
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"EventCode": "0x8",
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"EventName": "DTLB_LOAD_MISSES.PDE_MISS",
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"SampleAfterValue": "200000",
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"UMask": "0x20"
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},
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{
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"BriefDescription": "DTLB second level hit",
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"Counter": "0,1,2,3",
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"EventCode": "0x8",
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"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
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"SampleAfterValue": "2000000",
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"UMask": "0x10"
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},
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{
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"BriefDescription": "DTLB load miss page walks complete",
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"Counter": "0,1,2,3",
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"EventCode": "0x8",
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"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
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"SampleAfterValue": "200000",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "DTLB misses",
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"Counter": "0,1,2,3",
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"EventCode": "0x49",
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"EventName": "DTLB_MISSES.ANY",
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"SampleAfterValue": "200000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "DTLB first level misses but second level hit",
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"Counter": "0,1,2,3",
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"EventCode": "0x49",
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"EventName": "DTLB_MISSES.STLB_HIT",
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"SampleAfterValue": "200000",
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"UMask": "0x10"
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},
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{
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"BriefDescription": "DTLB miss page walks",
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"Counter": "0,1,2,3",
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"EventCode": "0x49",
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"EventName": "DTLB_MISSES.WALK_COMPLETED",
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"SampleAfterValue": "200000",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "ITLB flushes",
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"Counter": "0,1,2,3",
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"EventCode": "0xAE",
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"EventName": "ITLB_FLUSH",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "ITLB miss",
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"Counter": "0,1,2,3",
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"EventCode": "0x85",
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"EventName": "ITLB_MISSES.ANY",
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"SampleAfterValue": "200000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "ITLB miss page walks",
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"Counter": "0,1,2,3",
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"EventCode": "0x85",
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"EventName": "ITLB_MISSES.WALK_COMPLETED",
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"SampleAfterValue": "200000",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",
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"Counter": "0,1,2,3",
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"EventCode": "0xC8",
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"EventName": "ITLB_MISS_RETIRED",
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"PEBS": "1",
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"SampleAfterValue": "200000",
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"UMask": "0x20"
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},
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{
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"BriefDescription": "Large ITLB hit",
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"Counter": "0,1,2,3",
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"EventCode": "0x82",
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"EventName": "LARGE_ITLB.HIT",
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"SampleAfterValue": "200000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Retired loads that miss the DTLB (Precise Event)",
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"Counter": "0,1,2,3",
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"EventCode": "0xCB",
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"EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
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"PEBS": "1",
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"SampleAfterValue": "200000",
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"UMask": "0x80"
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},
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{
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"BriefDescription": "Retired stores that miss the DTLB (Precise Event)",
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"Counter": "0,1,2,3",
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"EventCode": "0xC",
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"EventName": "MEM_STORE_RETIRED.DTLB_MISS",
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"PEBS": "1",
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"SampleAfterValue": "200000",
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"UMask": "0x1"
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}
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]
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