mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-02 16:44:59 +00:00
025cce253b
Add counter information necessary for optimizing event grouping the
perf tool.
The most recent RFC patch set using this information:
https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/
The information was added in:
475892a969
and later patches.
Co-authored-by: Weilin Wang <weilin.wang@intel.com>
Co-authored-by: Caleb Biggers <caleb.biggers@intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/r/20240620181752.3945845-22-irogers@google.com
59 lines
2.1 KiB
JSON
59 lines
2.1 KiB
JSON
[
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{
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"BriefDescription": "Counts the number of times the front end resteers for any branch as a result of another branch handling mechanism in the front end.",
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"Counter": "0,1",
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"EventCode": "0xE6",
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"EventName": "BACLEARS.ALL",
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"SampleAfterValue": "200003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts the number of times the front end resteers for conditional branches as a result of another branch handling mechanism in the front end.",
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"Counter": "0,1",
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"EventCode": "0xE6",
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"EventName": "BACLEARS.COND",
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"SampleAfterValue": "200003",
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"UMask": "0x10"
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},
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{
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"BriefDescription": "Counts the number of times the front end resteers for RET branches as a result of another branch handling mechanism in the front end.",
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"Counter": "0,1",
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"EventCode": "0xE6",
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"EventName": "BACLEARS.RETURN",
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"SampleAfterValue": "200003",
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"UMask": "0x8"
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},
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{
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"BriefDescription": "Counts all instruction fetches, including uncacheable fetches.",
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"Counter": "0,1",
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"EventCode": "0x80",
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"EventName": "ICACHE.ACCESSES",
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"SampleAfterValue": "200003",
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"UMask": "0x3"
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},
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{
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"BriefDescription": "Counts all instruction fetches that hit the instruction cache.",
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"Counter": "0,1",
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"EventCode": "0x80",
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"EventName": "ICACHE.HIT",
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"SampleAfterValue": "200003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstanding.",
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"Counter": "0,1",
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"EventCode": "0x80",
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"EventName": "ICACHE.MISSES",
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"SampleAfterValue": "200003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Counts the number of times the MSROM starts a flow of uops.",
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"Counter": "0,1",
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"EventCode": "0xE7",
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"EventName": "MS_DECODED.MS_ENTRY",
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"SampleAfterValue": "200003",
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"UMask": "0x1"
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}
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]
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