mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-02 16:44:59 +00:00
025cce253b
Add counter information necessary for optimizing event grouping the
perf tool.
The most recent RFC patch set using this information:
https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/
The information was added in:
475892a969
and later patches.
Co-authored-by: Weilin Wang <weilin.wang@intel.com>
Co-authored-by: Caleb Biggers <caleb.biggers@intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/r/20240620181752.3945845-22-irogers@google.com
30 lines
1.8 KiB
JSON
30 lines
1.8 KiB
JSON
[
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{
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"BriefDescription": "Counts the number of floating operations retired that required microcode assists",
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"Counter": "0,1",
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"EventCode": "0xC3",
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"EventName": "MACHINE_CLEARS.FP_ASSIST",
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"PublicDescription": "This event counts the number of times that the pipeline stalled due to FP operations needing assists.",
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"SampleAfterValue": "200003",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "Counts the number of packed SSE, AVX, AVX2, AVX-512 micro-ops (both floating point and integer) except for loads (memory-to-register mov-type micro-ops), packed byte and word multiplies.",
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"Counter": "0,1",
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"EventCode": "0xC2",
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"EventName": "UOPS_RETIRED.PACKED_SIMD",
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"PublicDescription": "The length of the packed operation (128bits, 256bits or 512bits) is not taken into account when updating the counter; all count the same (+1). \r\nMask (k) registers are ignored. For example: a micro-op operating with a mask that only enables one element or even zero elements will still trigger this counter (+1)\r\nThis event is defined at the micro-op level and not instruction level. Most instructions are implemented with one micro-op but not all.",
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"SampleAfterValue": "200003",
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"UMask": "0x40"
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},
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{
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"BriefDescription": "Counts the number of scalar SSE, AVX, AVX2, AVX-512 micro-ops except for loads (memory-to-register mov-type micro ops), division, sqrt.",
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"Counter": "0,1",
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"EventCode": "0xC2",
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"EventName": "UOPS_RETIRED.SCALAR_SIMD",
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"PublicDescription": "This event is defined at the micro-op level and not instruction level. Most instructions are implemented with one micro-op but not all.",
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"SampleAfterValue": "200003",
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"UMask": "0x20"
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}
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]
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