mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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e7972827fc
Update TMA metrics from 4.8 to 5.02. Move INSTS_WRITTEN_TO_IQ.INSTS to the frontend topic. Signed-off-by: Ian Rogers <irogers@google.com> Tested-by: Thomas Falcon <thomas.falcon@intel.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Andreas Färber <afaerber@suse.de> Cc: Caleb Biggers <caleb.biggers@intel.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Perry Taylor <perry.taylor@intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Weilin Wang <weilin.wang@intel.com> Link: https://lore.kernel.org/r/20250328175006.43110-21-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
45 lines
1.6 KiB
JSON
45 lines
1.6 KiB
JSON
[
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{
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"BriefDescription": "Unhalted core cycles when the thread is in ring 0.",
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"Counter": "0,1,2,3",
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"EventCode": "0x5C",
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"EventName": "CPL_CYCLES.RING0",
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"SampleAfterValue": "2000003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Number of intervals between processor halts while thread is in ring 0.",
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"Counter": "0,1,2,3",
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"CounterMask": "1",
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"EdgeDetect": "1",
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"EventCode": "0x5C",
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"EventName": "CPL_CYCLES.RING0_TRANS",
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"SampleAfterValue": "100007",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.",
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"Counter": "0,1,2,3",
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"EventCode": "0x5C",
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"EventName": "CPL_CYCLES.RING123",
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"SampleAfterValue": "2000003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .",
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"Counter": "0,1,2,3",
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"EventCode": "0x4E",
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"EventName": "HW_PRE_REQ.DL1_MISS",
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"SampleAfterValue": "2000003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.",
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"Counter": "0,1,2,3",
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"EventCode": "0x63",
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"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
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"SampleAfterValue": "2000003",
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"UMask": "0x1"
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}
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]
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