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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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4ecf9eab4a
Update event topics, addition of PDIST counter into descriptions, metrics to be generated from the TMA spreadsheet and other small clean ups. Signed-off-by: Ian Rogers <irogers@google.com> Tested-by: Thomas Falcon <thomas.falcon@intel.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Andreas Färber <afaerber@suse.de> Cc: Caleb Biggers <caleb.biggers@intel.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Perry Taylor <perry.taylor@intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Weilin Wang <weilin.wang@intel.com> Link: https://lore.kernel.org/r/20250328175006.43110-12-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
33 lines
1.3 KiB
JSON
33 lines
1.3 KiB
JSON
[
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{
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"BriefDescription": "ASSISTS.PAGE_FAULT",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc1",
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"EventName": "ASSISTS.PAGE_FAULT",
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"PublicDescription": "ASSISTS.PAGE_FAULT Available PDIST counters: 0",
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"SampleAfterValue": "1000003",
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"UMask": "0x8"
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},
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{
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"BriefDescription": "Counts streaming stores that have any type of response.",
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"Counter": "0,1,2,3",
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"EventCode": "0x2A,0x2B",
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"EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x10800",
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"PublicDescription": "Counts streaming stores that have any type of response. Available PDIST counters: 0",
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"SampleAfterValue": "100003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Cycles the uncore cannot take further requests",
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"Counter": "0,1,2,3",
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"CounterMask": "1",
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"EventCode": "0x2d",
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"EventName": "XQ.FULL_CYCLES",
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"PublicDescription": "number of cycles when the thread is active and the uncore cannot take any further requests (for example prefetches, loads or stores initiated by the Core that miss the L2 cache). Available PDIST counters: 0",
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"SampleAfterValue": "1000003",
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"UMask": "0x1"
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}
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]
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