mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-02 16:44:59 +00:00
c4ba122a7e
Update event topic of OCR.DEMAND_DATA_RD.ANY_RESPONSE and OCR.DEMAND_RFO.ANY_RESPONSE to be cache. Add PDIST counter into descriptions. Signed-off-by: Ian Rogers <irogers@google.com> Tested-by: Thomas Falcon <thomas.falcon@intel.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Andreas Färber <afaerber@suse.de> Cc: Caleb Biggers <caleb.biggers@intel.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Perry Taylor <perry.taylor@intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Weilin Wang <weilin.wang@intel.com> Link: https://lore.kernel.org/r/20250328175006.43110-10-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
180 lines
9.8 KiB
JSON
180 lines
9.8 KiB
JSON
[
|
|
{
|
|
"BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x2e",
|
|
"EventName": "LONGEST_LAT_CACHE.MISS",
|
|
"PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x41"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0x2e",
|
|
"EventName": "LONGEST_LAT_CACHE.REFERENCE",
|
|
"PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x4f"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of load ops retired.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xd0",
|
|
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
|
|
"PublicDescription": "Counts the number of load ops retired. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x81"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of store ops retired.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xd0",
|
|
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
|
|
"PublicDescription": "Counts the number of store ops retired. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x82"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
|
|
"Counter": "0,1",
|
|
"EventCode": "0xd0",
|
|
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024",
|
|
"MSRIndex": "0x3F6",
|
|
"MSRValue": "0x400",
|
|
"PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x5"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
|
|
"Counter": "0,1",
|
|
"EventCode": "0xd0",
|
|
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
|
|
"MSRIndex": "0x3F6",
|
|
"MSRValue": "0x80",
|
|
"PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x5"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
|
|
"Counter": "0,1",
|
|
"EventCode": "0xd0",
|
|
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
|
|
"MSRIndex": "0x3F6",
|
|
"MSRValue": "0x10",
|
|
"PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x5"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
|
|
"Counter": "0,1",
|
|
"EventCode": "0xd0",
|
|
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048",
|
|
"MSRIndex": "0x3F6",
|
|
"MSRValue": "0x800",
|
|
"PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x5"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
|
|
"Counter": "0,1",
|
|
"EventCode": "0xd0",
|
|
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
|
|
"MSRIndex": "0x3F6",
|
|
"MSRValue": "0x100",
|
|
"PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x5"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
|
|
"Counter": "0,1",
|
|
"EventCode": "0xd0",
|
|
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
|
|
"MSRIndex": "0x3F6",
|
|
"MSRValue": "0x20",
|
|
"PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x5"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
|
|
"Counter": "0,1",
|
|
"EventCode": "0xd0",
|
|
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
|
|
"MSRIndex": "0x3F6",
|
|
"MSRValue": "0x4",
|
|
"PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x5"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
|
|
"Counter": "0,1",
|
|
"EventCode": "0xd0",
|
|
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
|
|
"MSRIndex": "0x3F6",
|
|
"MSRValue": "0x200",
|
|
"PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x5"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
|
|
"Counter": "0,1",
|
|
"EventCode": "0xd0",
|
|
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
|
|
"MSRIndex": "0x3F6",
|
|
"MSRValue": "0x40",
|
|
"PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x5"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.",
|
|
"Counter": "0,1",
|
|
"EventCode": "0xd0",
|
|
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",
|
|
"MSRIndex": "0x3F6",
|
|
"MSRValue": "0x8",
|
|
"PublicDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x5"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xd0",
|
|
"EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",
|
|
"PublicDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES Available PDIST counters: 0,1",
|
|
"SampleAfterValue": "1000003",
|
|
"UMask": "0x6"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts demand data reads that have any type of response.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xB7",
|
|
"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
|
|
"MSRIndex": "0x1a6,0x1a7",
|
|
"MSRValue": "0x10001",
|
|
"PublicDescription": "Counts demand data reads that have any type of response. Available PDIST counters: 0",
|
|
"SampleAfterValue": "100003",
|
|
"UMask": "0x1"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
|
|
"Counter": "0,1,2,3,4,5,6,7",
|
|
"EventCode": "0xB7",
|
|
"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
|
|
"MSRIndex": "0x1a6,0x1a7",
|
|
"MSRValue": "0x10002",
|
|
"PublicDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response. Available PDIST counters: 0",
|
|
"SampleAfterValue": "100003",
|
|
"UMask": "0x1"
|
|
}
|
|
]
|