mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-01 23:46:45 +00:00
19121e877c
Add counter information necessary for optimizing event grouping the
perf tool.
The most recent RFC patch set using this information:
https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/
The information was added in:
475892a969
and later patches.
Co-authored-by: Weilin Wang <weilin.wang@intel.com>
Co-authored-by: Caleb Biggers <caleb.biggers@intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
Link: https://lore.kernel.org/r/20240620181752.3945845-4-irogers@google.com
92 lines
2.7 KiB
JSON
92 lines
2.7 KiB
JSON
[
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{
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"BriefDescription": "BACLEARS asserted.",
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"Counter": "0,1",
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"EventCode": "0xE6",
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"EventName": "BACLEARS.ANY",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Cycles during which instruction fetches are stalled.",
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"Counter": "0,1",
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"EventCode": "0x86",
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"EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Decode stall due to IQ full",
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"Counter": "0,1",
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"EventCode": "0x87",
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"EventName": "DECODE_STALL.IQ_FULL",
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"SampleAfterValue": "2000000",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Decode stall due to PFB empty",
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"Counter": "0,1",
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"EventCode": "0x87",
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"EventName": "DECODE_STALL.PFB_EMPTY",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Instruction fetches.",
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"Counter": "0,1",
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"EventCode": "0x80",
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"EventName": "ICACHE.ACCESSES",
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"SampleAfterValue": "200000",
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"UMask": "0x3"
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},
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{
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"BriefDescription": "Icache hit",
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"Counter": "0,1",
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"EventCode": "0x80",
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"EventName": "ICACHE.HIT",
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"SampleAfterValue": "200000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Icache miss",
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"Counter": "0,1",
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"EventCode": "0x80",
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"EventName": "ICACHE.MISSES",
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"SampleAfterValue": "200000",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "All Instructions decoded",
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"Counter": "0,1",
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"EventCode": "0xAA",
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"EventName": "MACRO_INSTS.ALL_DECODED",
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"SampleAfterValue": "2000000",
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"UMask": "0x3"
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},
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{
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"BriefDescription": "CISC macro instructions decoded",
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"Counter": "0,1",
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"EventCode": "0xAA",
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"EventName": "MACRO_INSTS.CISC_DECODED",
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"SampleAfterValue": "2000000",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Non-CISC macro instructions decoded",
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"Counter": "0,1",
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"EventCode": "0xAA",
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"EventName": "MACRO_INSTS.NON_CISC_DECODED",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.",
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"Counter": "0,1",
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"CounterMask": "1",
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"EventCode": "0xA9",
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"EventName": "UOPS.MS_CYCLES",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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}
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]
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