mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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fd3dfa4b82
Update events from v1.07 to v1.08. Update event topics, addition of PIST counter into descriptions, metrics to be generated from the TMA spreadsheet and other small clean ups. Signed-off-by: Ian Rogers <irogers@google.com> Tested-by: Thomas Falcon <thomas.falcon@intel.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Andreas Färber <afaerber@suse.de> Cc: Caleb Biggers <caleb.biggers@intel.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Perry Taylor <perry.taylor@intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Weilin Wang <weilin.wang@intel.com> Link: https://lore.kernel.org/r/20250328175006.43110-4-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
91 lines
4.2 KiB
JSON
91 lines
4.2 KiB
JSON
[
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{
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"BriefDescription": "Count all other hardware assists or traps that are not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and A/D assists who are counted by dedicated sub-events.",
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"Counter": "0,1,2,3,4,5,6,7,8,9",
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"EventCode": "0xc1",
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"EventName": "ASSISTS.HARDWARE",
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"PublicDescription": "Count all other hardware assists or traps that are not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and A/D assists who are counted by dedicated sub-events. This includes, but not limited to, assists at EXE or MEM uop writeback like AVX* load/store/gather/scatter (non-FP GSSE-assist ) , assists generated by ROB like PEBS and RTIT, Uncore trap, RAR (Remote Action Request) and CET (Control flow Enforcement Technology) assists.",
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"SampleAfterValue": "100003",
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"UMask": "0x4",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "ASSISTS.PAGE_FAULT",
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"Counter": "0,1,2,3,4,5,6,7,8,9",
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"EventCode": "0xc1",
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"EventName": "ASSISTS.PAGE_FAULT",
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"SampleAfterValue": "1000003",
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"UMask": "0x8",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "This event is deprecated. [This event is alias to MISC_RETIRED.LBR_INSERTS]",
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"Counter": "0,1,2,3,4,5,6,7",
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"Deprecated": "1",
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"EventCode": "0xe4",
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"EventName": "LBR_INSERTS.ANY",
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"SampleAfterValue": "1000003",
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"UMask": "0x1",
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"Unit": "cpu_lowpower"
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},
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{
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"BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that have any type of response.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xB7",
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"EventName": "OCR.FULL_STREAMING_WR.ANY_RESPONSE",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x800000010000",
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"PublicDescription": "Counts streaming stores which modify a full 64 byte cacheline that have any type of response. Available PDIST counters: 0",
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"SampleAfterValue": "100003",
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"UMask": "0x1",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that have any type of response.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xB7",
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"EventName": "OCR.PARTIAL_STREAMING_WR.ANY_RESPONSE",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x400000010000",
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"PublicDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that have any type of response. Available PDIST counters: 0",
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"SampleAfterValue": "100003",
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"UMask": "0x1",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts streaming stores that have any type of response.",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xB7",
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"EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x10800",
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"PublicDescription": "Counts streaming stores that have any type of response. Available PDIST counters: 0",
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"SampleAfterValue": "100003",
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"UMask": "0x1",
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"Unit": "cpu_atom"
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},
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{
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"BriefDescription": "Counts streaming stores that have any type of response.",
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"Counter": "0,1,2,3",
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"EventCode": "0x2A,0x2B",
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"EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x10800",
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"PublicDescription": "Counts streaming stores that have any type of response. Available PDIST counters: 0",
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"SampleAfterValue": "100003",
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"UMask": "0x1",
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"Unit": "cpu_core"
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},
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{
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"BriefDescription": "Cycles the uncore cannot take further requests",
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"Counter": "0,1,2,3,4,5,6,7,8,9",
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"CounterMask": "1",
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"EventCode": "0x2d",
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"EventName": "XQ.FULL",
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"PublicDescription": "number of cycles when the thread is active and the uncore cannot take any further requests (for example prefetches, loads or stores initiated by the Core that miss the L2 cache).",
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"SampleAfterValue": "1000003",
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"UMask": "0x1",
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"Unit": "cpu_core"
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}
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]
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