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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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dc082ae618
Add uncore events taken from Section 1.5 "L3 Cache Performance Monitor Counters" and Section 2 "UMC Performance Monitors" of the Performance Monitor Counters for AMD Family 1Ah Model 00h-0Fh Processors document available at the link below. This constitutes events which capture L3 cache and UMC command activity. Reviewed-by: Ian Rogers <irogers@google.com> Signed-off-by: Sandipan Das <sandipan.das@amd.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ananth Narayan <ananth.narayan@amd.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ravi Bangoria <ravi.bangoria@amd.com> Cc: Stephane Eranian <eranian@google.com> Link: https://bugzilla.kernel.org/attachment.cgi?id=305974 Link: https://lore.kernel.org/r/e11e8d9d1af34a0fb565fc9d1c4a05f569c39ddc.1714717230.git.sandipan.das@amd.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
102 lines
2.5 KiB
JSON
102 lines
2.5 KiB
JSON
[
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{
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"EventName": "umc_mem_clk",
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"PublicDescription": "Number of memory clock (MEMCLK) cycles.",
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"EventCode": "0x00",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_act_cmd.all",
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"PublicDescription": "Number of ACTIVATE commands sent.",
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"EventCode": "0x05",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_act_cmd.rd",
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"PublicDescription": "Number of ACTIVATE commands sent for reads.",
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"EventCode": "0x05",
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"RdWrMask": "0x1",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_act_cmd.wr",
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"PublicDescription": "Number of ACTIVATE commands sent for writes.",
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"EventCode": "0x05",
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"RdWrMask": "0x2",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_pchg_cmd.all",
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"PublicDescription": "Number of PRECHARGE commands sent.",
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"EventCode": "0x06",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_pchg_cmd.rd",
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"PublicDescription": "Number of PRECHARGE commands sent for reads.",
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"EventCode": "0x06",
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"RdWrMask": "0x1",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_pchg_cmd.wr",
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"PublicDescription": "Number of PRECHARGE commands sent for writes.",
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"EventCode": "0x06",
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"RdWrMask": "0x2",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_cas_cmd.all",
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"PublicDescription": "Number of CAS commands sent.",
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"EventCode": "0x0a",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_cas_cmd.rd",
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"PublicDescription": "Number of CAS commands sent for reads.",
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"EventCode": "0x0a",
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"RdWrMask": "0x1",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_cas_cmd.wr",
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"PublicDescription": "Number of CAS commands sent for writes.",
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"EventCode": "0x0a",
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"RdWrMask": "0x2",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_data_slot_clks.all",
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"PublicDescription": "Number of clock cycles used by the data bus.",
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"EventCode": "0x14",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_data_slot_clks.rd",
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"PublicDescription": "Number of clock cycles used by the data bus for reads.",
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"EventCode": "0x14",
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"RdWrMask": "0x1",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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},
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{
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"EventName": "umc_data_slot_clks.wr",
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"PublicDescription": "Number of clock cycles used by the data bus for writes.",
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"EventCode": "0x14",
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"RdWrMask": "0x2",
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"PerPkg": "1",
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"Unit": "UMCPMC"
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}
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]
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