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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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45c072f253
Add core events taken from Section 1.4 "Core Performance Monitor Counters" of the Performance Monitor Counters for AMD Family 1Ah Model 00h-0Fh Processors document available at the link below. This constitutes events which capture information on op dispatch, execution and retirement, branch prediction, L1 and L2 cache activity, TLB activity, etc. Reviewed-by: Ian Rogers <irogers@google.com> Signed-off-by: Sandipan Das <sandipan.das@amd.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ananth Narayan <ananth.narayan@amd.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ravi Bangoria <ravi.bangoria@amd.com> Cc: Stephane Eranian <eranian@google.com> Link: https://bugzilla.kernel.org/attachment.cgi?id=305974 Link: https://lore.kernel.org/r/668d194241bf0d42dc37f1c5af8131069a0bd82c.1714717230.git.sandipan.das@amd.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
267 lines
9.4 KiB
JSON
267 lines
9.4 KiB
JSON
[
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{
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"EventName": "l2_request_g1.group2",
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"EventCode": "0x60",
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"BriefDescription": "L2 cache requests of non-cacheable type (non-cached data and instructions reads, self-modifying code checks).",
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"UMask": "0x01"
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},
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{
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"EventName": "l2_request_g1.l2_hw_pf",
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"EventCode": "0x60",
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"BriefDescription": "L2 cache requests: from hardware prefetchers to prefetch directly into L2 (hit or miss).",
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"UMask": "0x02"
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},
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{
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"EventName": "l2_request_g1.prefetch_l2_cmd",
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"EventCode": "0x60",
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"BriefDescription": "L2 cache requests: prefetch directly into L2.",
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"UMask": "0x04"
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},
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{
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"EventName": "l2_request_g1.cacheable_ic_read",
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"EventCode": "0x60",
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"BriefDescription": "L2 cache requests: instruction cache reads.",
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"UMask": "0x10"
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},
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{
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"EventName": "l2_request_g1.ls_rd_blk_c_s",
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"EventCode": "0x60",
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"BriefDescription": "L2 cache requests: data cache shared reads.",
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"UMask": "0x20"
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},
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{
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"EventName": "l2_request_g1.rd_blk_x",
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"EventCode": "0x60",
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"BriefDescription": "L2 cache requests: data cache stores.",
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"UMask": "0x40"
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},
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{
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"EventName": "l2_request_g1.rd_blk_l",
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"EventCode": "0x60",
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"BriefDescription": "L2 cache requests: data cache reads including hardware and software prefetch.",
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"UMask": "0x80"
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},
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{
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"EventName": "l2_request_g1.all_dc",
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"EventCode": "0x60",
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"BriefDescription": "L2 cache requests of common types from L1 data cache (including prefetches).",
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"UMask": "0xe0"
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},
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{
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"EventName": "l2_request_g1.all_no_prefetch",
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"EventCode": "0x60",
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"BriefDescription": "L2 cache requests of common types not including prefetches.",
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"UMask": "0xf1"
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},
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{
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"EventName": "l2_request_g1.all",
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"EventCode": "0x60",
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"BriefDescription": "L2 cache requests of all types.",
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"UMask": "0xf7"
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},
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{
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"EventName": "l2_request_g2.ls_rd_sized_nc",
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"EventCode": "0x61",
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"BriefDescription": "L2 cache requests: non-coherent, non-cacheable LS sized reads.",
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"UMask": "0x20"
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},
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{
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"EventName": "l2_request_g2.ls_rd_sized",
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"EventCode": "0x61",
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"BriefDescription": "L2 cache requests: coherent, non-cacheable LS sized reads.",
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"UMask": "0x40"
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},
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{
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"EventName": "l2_wcb_req.wcb_close",
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"EventCode": "0x63",
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"BriefDescription": "Write Combining Buffer (WCB) closures.",
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"UMask": "0x20"
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},
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{
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"EventName": "l2_cache_req_stat.ic_fill_miss",
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"EventCode": "0x64",
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"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: instruction cache request miss in L2.",
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"UMask": "0x01"
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},
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{
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"EventName": "l2_cache_req_stat.ic_fill_hit_s",
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"EventCode": "0x64",
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"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: instruction cache hit non-modifiable line in L2.",
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"UMask": "0x02"
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},
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{
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"EventName": "l2_cache_req_stat.ic_fill_hit_x",
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"EventCode": "0x64",
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"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: instruction cache hit modifiable line in L2.",
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"UMask": "0x04"
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},
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{
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"EventName": "l2_cache_req_stat.ic_hit_in_l2",
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"EventCode": "0x64",
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"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for instruction cache hits.",
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"UMask": "0x06"
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},
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{
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"EventName": "l2_cache_req_stat.ic_access_in_l2",
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"EventCode": "0x64",
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"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for instruction cache access.",
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"UMask": "0x07"
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},
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{
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"EventName": "l2_cache_req_stat.ls_rd_blk_c",
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"EventCode": "0x64",
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"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache request miss in L2.",
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"UMask": "0x08"
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},
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{
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"EventName": "l2_cache_req_stat.ic_dc_miss_in_l2",
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"EventCode": "0x64",
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"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data and instruction cache misses.",
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"UMask": "0x09"
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},
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{
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"EventName": "l2_cache_req_stat.ls_rd_blk_x",
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"EventCode": "0x64",
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"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache store or state change hit in L2.",
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"UMask": "0x10"
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},
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{
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"EventName": "l2_cache_req_stat.ls_rd_blk_l_hit_s",
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"EventCode": "0x64",
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"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache read hit non-modifiable line in L2.",
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"UMask": "0x20"
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},
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{
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"EventName": "l2_cache_req_stat.ls_rd_blk_l_hit_x",
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"EventCode": "0x64",
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"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache read hit modifiable line in L2.",
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"UMask": "0x40"
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},
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{
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"EventName": "l2_cache_req_stat.ls_rd_blk_cs",
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"EventCode": "0x64",
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"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache shared read hit in L2.",
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"UMask": "0x80"
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},
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{
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"EventName": "l2_cache_req_stat.dc_hit_in_l2",
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"EventCode": "0x64",
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"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data cache hits.",
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"UMask": "0xf0"
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},
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{
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"EventName": "l2_cache_req_stat.ic_dc_hit_in_l2",
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"EventCode": "0x64",
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"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data and instruction cache hits.",
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"UMask": "0xf6"
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},
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{
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"EventName": "l2_cache_req_stat.dc_access_in_l2",
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"EventCode": "0x64",
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"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data cache access.",
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"UMask": "0xf8"
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},
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{
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"EventName": "l2_cache_req_stat.all",
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"EventCode": "0x64",
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"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data and instruction cache access.",
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"UMask": "0xff"
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},
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{
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"EventName": "l2_pf_hit_l2.l2_hwpf",
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"EventCode": "0x70",
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"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache and are generated from L2 hardware prefetchers.",
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"UMask": "0x1f"
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},
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{
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"EventName": "l2_pf_hit_l2.l1_dc_hwpf",
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"EventCode": "0x70",
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"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache and are generated from L1 data hardware prefetchers.",
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"UMask": "0xe0"
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},
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{
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"EventName": "l2_pf_hit_l2.l1_dc_l2_hwpf",
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"EventCode": "0x70",
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"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache and are generated from L1 data and L2 hardware prefetchers.",
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"UMask": "0xff"
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},
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{
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"EventName": "l2_pf_miss_l2_hit_l3.l2_hwpf",
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"EventCode": "0x71",
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"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache but hit in the L3 cache and are generated from L2 hardware prefetchers.",
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"UMask": "0x1f"
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},
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{
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"EventName": "l2_pf_miss_l2_hit_l3.l1_dc_hwpf",
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"EventCode": "0x71",
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"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache but hit in the L3 cache and are generated from L1 data hardware prefetchers.",
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"UMask": "0xe0"
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},
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{
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"EventName": "l2_pf_miss_l2_hit_l3.l1_dc_l2_hwpf",
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"EventCode": "0x71",
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"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache but hit in the L3 cache and are generated from L1 data and L2 hardware prefetchers.",
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"UMask": "0xff"
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},
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{
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"EventName": "l2_pf_miss_l2_l3.l2_hwpf",
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"EventCode": "0x72",
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"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 as well as the L3 caches and are generated from L2 hardware prefetchers.",
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"UMask": "0x1f"
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},
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{
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"EventName": "l2_pf_miss_l2_l3.l1_dc_hwpf",
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"EventCode": "0x72",
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"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 as well as the L3 caches and are generated from L1 data hardware prefetchers.",
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"UMask": "0xe0"
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},
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{
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"EventName": "l2_pf_miss_l2_l3.l1_dc_l2_hwpf",
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"EventCode": "0x72",
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"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 as well as the L3 caches and are generated from L1 data and L2 hardware prefetchers.",
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"UMask": "0xff"
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},
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{
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"EventName": "l2_fill_rsp_src.local_ccx",
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"EventCode": "0x165",
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"BriefDescription": "L2 cache fills from L3 cache or different L2 cache in the same CCX.",
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"UMask": "0x02"
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},
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{
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"EventName": "l2_fill_rsp_src.near_cache",
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"EventCode": "0x165",
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"BriefDescription": "L2 cache fills from cache of another CCX when the address was in the same NUMA node.",
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"UMask": "0x04"
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},
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{
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"EventName": "l2_fill_rsp_src.dram_io_near",
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"EventCode": "0x165",
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"BriefDescription": "L2 cache fills from either DRAM or MMIO in the same NUMA node.",
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"UMask": "0x08"
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},
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{
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"EventName": "l2_fill_rsp_src.far_cache",
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"EventCode": "0x165",
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"BriefDescription": "L2 cache fills from cache of another CCX when the address was in a different NUMA node.",
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"UMask": "0x10"
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},
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{
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"EventName": "l2_fill_rsp_src.dram_io_far",
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"EventCode": "0x165",
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"BriefDescription": "L2 cache fills from either DRAM or MMIO in a different NUMA node (same or different socket).",
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"UMask": "0x40"
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},
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{
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"EventName": "l2_fill_rsp_src.alternate_memories",
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"EventCode": "0x165",
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"BriefDescription": "L2 cache fills from extension memory.",
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"UMask": "0x80"
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},
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{
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"EventName": "l2_fill_rsp_src.all",
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"EventCode": "0x165",
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"BriefDescription": "L2 cache fills from all types of data sources.",
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"UMask": "0xde"
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}
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]
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