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45c072f253
Add core events taken from Section 1.4 "Core Performance Monitor Counters" of the Performance Monitor Counters for AMD Family 1Ah Model 00h-0Fh Processors document available at the link below. This constitutes events which capture information on op dispatch, execution and retirement, branch prediction, L1 and L2 cache activity, TLB activity, etc. Reviewed-by: Ian Rogers <irogers@google.com> Signed-off-by: Sandipan Das <sandipan.das@amd.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ananth Narayan <ananth.narayan@amd.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ravi Bangoria <ravi.bangoria@amd.com> Cc: Stephane Eranian <eranian@google.com> Link: https://bugzilla.kernel.org/attachment.cgi?id=305974 Link: https://lore.kernel.org/r/668d194241bf0d42dc37f1c5af8131069a0bd82c.1714717230.git.sandipan.das@amd.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
73 lines
2.2 KiB
JSON
73 lines
2.2 KiB
JSON
[
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{
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"EventName": "ic_cache_fill_l2",
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"EventCode": "0x82",
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"BriefDescription": "Instruction cache lines (64 bytes) fulfilled from the L2 cache."
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},
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{
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"EventName": "ic_cache_fill_sys",
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"EventCode": "0x83",
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"BriefDescription": "Instruction cache lines (64 bytes) fulfilled from system memory or another cache."
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},
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{
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"EventName": "ic_fetch_ibs_events.fetch_tagged",
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"EventCode": "0x188",
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"BriefDescription": "Fetches tagged by Fetch IBS. Not all tagged fetches result in a valid sample and an IBS interrupt.",
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"UMask": "0x02"
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},
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{
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"EventName": "ic_fetch_ibs_events.sample_discarded",
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"EventCode": "0x188",
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"BriefDescription": "Fetches discarded after being tagged by Fetch IBS due to reasons other than IBS filtering.",
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"UMask": "0x04"
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},
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{
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"EventName": "ic_fetch_ibs_events.sample_filtered",
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"EventCode": "0x188",
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"BriefDescription": "Fetches discarded after being tagged by Fetch IBS due to IBS filtering.",
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"UMask": "0x08"
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},
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{
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"EventName": "ic_fetch_ibs_events.sample_valid",
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"EventCode": "0x188",
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"BriefDescription": "Fetches tagged by Fetch IBS that result in a valid sample and an IBS interrupt.",
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"UMask": "0x10"
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},
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{
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"EventName": "ic_tag_hit_miss.instruction_cache_hit",
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"EventCode": "0x18e",
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"BriefDescription": "Instruction cache hits.",
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"UMask": "0x07"
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},
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{
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"EventName": "ic_tag_hit_miss.instruction_cache_miss",
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"EventCode": "0x18e",
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"BriefDescription": "Instruction cache misses.",
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"UMask": "0x18"
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},
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{
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"EventName": "ic_tag_hit_miss.all_instruction_cache_accesses",
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"EventCode": "0x18e",
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"BriefDescription": "Instruction cache accesses of all types.",
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"UMask": "0x1f"
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},
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{
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"EventName": "op_cache_hit_miss.op_cache_hit",
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"EventCode": "0x28f",
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"BriefDescription": "Op cache hits.",
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"UMask": "0x03"
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},
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{
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"EventName": "op_cache_hit_miss.op_cache_miss",
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"EventCode": "0x28f",
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"BriefDescription": "Op cache misses.",
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"UMask": "0x04"
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},
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{
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"EventName": "op_cache_hit_miss.all_op_cache_accesses",
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"EventCode": "0x28f",
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"BriefDescription": "Op cache accesses of all types.",
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"UMask": "0x07"
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}
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]
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