mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-02 16:44:59 +00:00
45c072f253
Add core events taken from Section 1.4 "Core Performance Monitor Counters" of the Performance Monitor Counters for AMD Family 1Ah Model 00h-0Fh Processors document available at the link below. This constitutes events which capture information on op dispatch, execution and retirement, branch prediction, L1 and L2 cache activity, TLB activity, etc. Reviewed-by: Ian Rogers <irogers@google.com> Signed-off-by: Sandipan Das <sandipan.das@amd.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ananth Narayan <ananth.narayan@amd.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ravi Bangoria <ravi.bangoria@amd.com> Cc: Stephane Eranian <eranian@google.com> Link: https://bugzilla.kernel.org/attachment.cgi?id=305974 Link: https://lore.kernel.org/r/668d194241bf0d42dc37f1c5af8131069a0bd82c.1714717230.git.sandipan.das@amd.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
94 lines
3.3 KiB
JSON
94 lines
3.3 KiB
JSON
[
|
|
{
|
|
"EventName": "bp_l1_tlb_miss_l2_tlb_hit",
|
|
"EventCode": "0x84",
|
|
"BriefDescription": "Instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
|
|
},
|
|
{
|
|
"EventName": "bp_l1_tlb_miss_l2_tlb_miss.if4k",
|
|
"EventCode": "0x85",
|
|
"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 4k pages.",
|
|
"UMask": "0x01"
|
|
},
|
|
{
|
|
"EventName": "bp_l1_tlb_miss_l2_tlb_miss.if2m",
|
|
"EventCode": "0x85",
|
|
"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 2M pages.",
|
|
"UMask": "0x02"
|
|
},
|
|
{
|
|
"EventName": "bp_l1_tlb_miss_l2_tlb_miss.if1g",
|
|
"EventCode": "0x85",
|
|
"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 1G pages.",
|
|
"UMask": "0x04"
|
|
},
|
|
{
|
|
"EventName": "bp_l1_tlb_miss_l2_tlb_miss.coalesced_4k",
|
|
"EventCode": "0x85",
|
|
"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
|
|
"UMask": "0x08"
|
|
},
|
|
{
|
|
"EventName": "bp_l1_tlb_miss_l2_tlb_miss.all",
|
|
"EventCode": "0x85",
|
|
"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for all page sizes.",
|
|
"UMask": "0x0f"
|
|
},
|
|
{
|
|
"EventName": "bp_l2_btb_correct",
|
|
"EventCode": "0x8b",
|
|
"BriefDescription": "L2 branch prediction overrides existing prediction (speculative)."
|
|
},
|
|
{
|
|
"EventName": "bp_dyn_ind_pred",
|
|
"EventCode": "0x8e",
|
|
"BriefDescription": "Dynamic indirect predictions (branch used the indirect predictor to make a prediction)."
|
|
},
|
|
{
|
|
"EventName": "bp_de_redirect",
|
|
"EventCode": "0x91",
|
|
"BriefDescription": "Number of times an early redirect is sent to branch predictor. This happens when either the decoder or dispatch logic is able to detect that the branch predictor needs to be redirected."
|
|
},
|
|
{
|
|
"EventName": "bp_l1_tlb_fetch_hit.if4k",
|
|
"EventCode": "0x94",
|
|
"BriefDescription": "Instruction fetches that hit in the L1 ITLB for 4k or coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
|
|
"UMask": "0x01"
|
|
},
|
|
{
|
|
"EventName": "bp_l1_tlb_fetch_hit.if2m",
|
|
"EventCode": "0x94",
|
|
"BriefDescription": "Instruction fetches that hit in the L1 ITLB for 2M pages.",
|
|
"UMask": "0x02"
|
|
},
|
|
{
|
|
"EventName": "bp_l1_tlb_fetch_hit.if1g",
|
|
"EventCode": "0x94",
|
|
"BriefDescription": "Instruction fetches that hit in the L1 ITLB for 1G pages.",
|
|
"UMask": "0x04"
|
|
},
|
|
{
|
|
"EventName": "bp_l1_tlb_fetch_hit.all",
|
|
"EventCode": "0x94",
|
|
"BriefDescription": "Instruction fetches that hit in the L1 ITLB for all page sizes.",
|
|
"UMask": "0x07"
|
|
},
|
|
{
|
|
"EventName": "bp_redirects.resync",
|
|
"EventCode": "0x9f",
|
|
"BriefDescription": "Redirects of the branch predictor caused by resyncs.",
|
|
"UMask": "0x01"
|
|
},
|
|
{
|
|
"EventName": "bp_redirects.ex_redir",
|
|
"EventCode": "0x9f",
|
|
"BriefDescription": "Redirects of the branch predictor caused by mispredicts.",
|
|
"UMask": "0x02"
|
|
},
|
|
{
|
|
"EventName": "bp_redirects.all",
|
|
"EventCode": "0x9f",
|
|
"BriefDescription": "Redirects of the branch predictor."
|
|
}
|
|
]
|