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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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658448281d
Add core events taken from Section 2.1.15.4 "Core Performance Monitor Counters" in the Processor Programming Reference (PPR) for AMD Family 19h Model 11h Revision B1 processors. This constitutes events which capture op dispatch, execution and retirement, branch prediction, L1 and L2 cache activity, TLB activity, etc. Signed-off-by: Sandipan Das <sandipan.das@amd.com> Acked-by: Ian Rogers <irogers@google.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ananth Narayan <ananth.narayan@amd.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Jirka Hladky <jhladky@redhat.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ravi Bangoria <ravi.bangoria@amd.com> Cc: Stephane Eranian <eranian@google.com> Link: https://lore.kernel.org/r/20221214082652.419965-2-sandipan.das@amd.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
175 lines
6.0 KiB
JSON
175 lines
6.0 KiB
JSON
[
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{
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"EventName": "ls_bad_status2.stli_other",
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"EventCode": "0x24",
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"BriefDescription": "Store-to-load conflicts (load unable to complete due to a non-forwardable conflict with an older store).",
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"UMask": "0x02"
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},
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{
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"EventName": "ls_dispatch.ld_dispatch",
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"EventCode": "0x29",
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"BriefDescription": "Number of memory load operations dispatched to the load-store unit.",
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"UMask": "0x01"
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},
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{
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"EventName": "ls_dispatch.store_dispatch",
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"EventCode": "0x29",
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"BriefDescription": "Number of memory store operations dispatched to the load-store unit.",
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"UMask": "0x02"
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},
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{
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"EventName": "ls_dispatch.ld_st_dispatch",
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"EventCode": "0x29",
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"BriefDescription": "Number of memory load-store operations dispatched to the load-store unit.",
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"UMask": "0x04"
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},
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{
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"EventName": "ls_stlf",
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"EventCode": "0x35",
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"BriefDescription": "Store-to-load-forward (STLF) hits."
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},
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{
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"EventName": "ls_st_commit_cancel2.st_commit_cancel_wcb_full",
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"EventCode": "0x37",
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"BriefDescription": "Non-cacheable store commits cancelled due to the non-cacheable commit buffer being full.",
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"UMask": "0x01"
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},
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{
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"EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit",
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"EventCode": "0x45",
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"BriefDescription": "L1 DTLB misses with L2 DTLB hits for 4k pages.",
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"UMask": "0x01"
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},
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{
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"EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit",
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"EventCode": "0x45",
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"BriefDescription": "L1 DTLB misses with L2 DTLB hits for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
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"UMask": "0x02"
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},
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{
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"EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit",
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"EventCode": "0x45",
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"BriefDescription": "L1 DTLB misses with L2 DTLB hits for 2M pages.",
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"UMask": "0x04"
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},
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{
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"EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit",
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"EventCode": "0x45",
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"BriefDescription": "L1 DTLB misses with L2 DTLB hits for 1G pages.",
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"UMask": "0x08"
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},
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{
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"EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss",
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"EventCode": "0x45",
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"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 4k pages.",
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"UMask": "0x10"
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},
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{
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"EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss",
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"EventCode": "0x45",
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"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
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"UMask": "0x20"
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},
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{
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"EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss",
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"EventCode": "0x45",
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"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 2M pages.",
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"UMask": "0x40"
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},
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{
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"EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss",
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"EventCode": "0x45",
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"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 1G pages.",
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"UMask": "0x80"
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},
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{
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"EventName": "ls_l1_d_tlb_miss.all_l2_miss",
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"EventCode": "0x45",
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"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for all page sizes.",
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"UMask": "0xf0"
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},
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{
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"EventName": "ls_l1_d_tlb_miss.all",
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"EventCode": "0x45",
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"BriefDescription": "L1 DTLB misses for all page sizes.",
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"UMask": "0xff"
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},
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{
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"EventName": "ls_misal_loads.ma64",
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"EventCode": "0x47",
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"BriefDescription": "64B misaligned (cacheline crossing) loads.",
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"UMask": "0x01"
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},
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{
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"EventName": "ls_misal_loads.ma4k",
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"EventCode": "0x47",
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"BriefDescription": "4kB misaligned (page crossing) loads.",
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"UMask": "0x02"
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},
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{
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"EventName": "ls_tlb_flush.all",
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"EventCode": "0x78",
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"BriefDescription": "All TLB Flushes.",
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"UMask": "0xff"
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},
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{
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"EventName": "bp_l1_tlb_miss_l2_tlb_hit",
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"EventCode": "0x84",
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"BriefDescription": "Instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
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},
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{
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"EventName": "bp_l1_tlb_miss_l2_tlb_miss.if4k",
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"EventCode": "0x85",
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"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 4k pages.",
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"UMask": "0x01"
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},
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{
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"EventName": "bp_l1_tlb_miss_l2_tlb_miss.if2m",
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"EventCode": "0x85",
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"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 2M pages.",
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"UMask": "0x02"
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},
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{
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"EventName": "bp_l1_tlb_miss_l2_tlb_miss.if1g",
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"EventCode": "0x85",
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"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 1G pages.",
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"UMask": "0x04"
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},
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{
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"EventName": "bp_l1_tlb_miss_l2_tlb_miss.coalesced_4k",
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"EventCode": "0x85",
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"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
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"UMask": "0x08"
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},
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{
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"EventName": "bp_l1_tlb_miss_l2_tlb_miss.all",
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"EventCode": "0x85",
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"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for all page sizes.",
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"UMask": "0x0f"
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},
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{
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"EventName": "bp_l1_tlb_fetch_hit.if4k",
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"EventCode": "0x94",
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"BriefDescription": "Instruction fetches that hit in the L1 ITLB for 4k or coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
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"UMask": "0x01"
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},
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{
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"EventName": "bp_l1_tlb_fetch_hit.if2m",
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"EventCode": "0x94",
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"BriefDescription": "Instruction fetches that hit in the L1 ITLB for 2M pages.",
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"UMask": "0x02"
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},
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{
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"EventName": "bp_l1_tlb_fetch_hit.if1g",
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"EventCode": "0x94",
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"BriefDescription": "Instruction fetches that hit in the L1 ITLB for 1G pages.",
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"UMask": "0x04"
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},
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{
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"EventName": "bp_l1_tlb_fetch_hit.all",
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"EventCode": "0x94",
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"BriefDescription": "Instruction fetches that hit in the L1 ITLB for all page sizes.",
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"UMask": "0x07"
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}
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]
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