mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-01 23:46:45 +00:00
658448281d
Add core events taken from Section 2.1.15.4 "Core Performance Monitor Counters" in the Processor Programming Reference (PPR) for AMD Family 19h Model 11h Revision B1 processors. This constitutes events which capture op dispatch, execution and retirement, branch prediction, L1 and L2 cache activity, TLB activity, etc. Signed-off-by: Sandipan Das <sandipan.das@amd.com> Acked-by: Ian Rogers <irogers@google.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ananth Narayan <ananth.narayan@amd.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Jirka Hladky <jhladky@redhat.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ravi Bangoria <ravi.bangoria@amd.com> Cc: Stephane Eranian <eranian@google.com> Link: https://lore.kernel.org/r/20221214082652.419965-2-sandipan.das@amd.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
83 lines
2.9 KiB
JSON
83 lines
2.9 KiB
JSON
[
|
|
{
|
|
"EventName": "bp_l2_btb_correct",
|
|
"EventCode": "0x8b",
|
|
"BriefDescription": "L2 branch prediction overrides existing prediction (speculative)."
|
|
},
|
|
{
|
|
"EventName": "bp_dyn_ind_pred",
|
|
"EventCode": "0x8e",
|
|
"BriefDescription": "Dynamic indirect predictions (branch used the indirect predictor to make a prediction)."
|
|
},
|
|
{
|
|
"EventName": "bp_de_redirect",
|
|
"EventCode": "0x91",
|
|
"BriefDescription": "Instruction decoder corrects the predicted target and resteers the branch predictor."
|
|
},
|
|
{
|
|
"EventName": "ex_ret_brn",
|
|
"EventCode": "0xc2",
|
|
"BriefDescription": "Retired branch instructions (all types of architectural control flow changes, including exceptions and interrupts)."
|
|
},
|
|
{
|
|
"EventName": "ex_ret_brn_misp",
|
|
"EventCode": "0xc3",
|
|
"BriefDescription": "Retired branch instructions mispredicted."
|
|
},
|
|
{
|
|
"EventName": "ex_ret_brn_tkn",
|
|
"EventCode": "0xc4",
|
|
"BriefDescription": "Retired taken branch instructions (all types of architectural control flow changes, including exceptions and interrupts)."
|
|
},
|
|
{
|
|
"EventName": "ex_ret_brn_tkn_misp",
|
|
"EventCode": "0xc5",
|
|
"BriefDescription": "Retired taken branch instructions mispredicted."
|
|
},
|
|
{
|
|
"EventName": "ex_ret_brn_far",
|
|
"EventCode": "0xc6",
|
|
"BriefDescription": "Retired far control transfers (far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts). Far control transfers are not subject to branch prediction."
|
|
},
|
|
{
|
|
"EventName": "ex_ret_near_ret",
|
|
"EventCode": "0xc8",
|
|
"BriefDescription": "Retired near returns (RET or RET Iw)."
|
|
},
|
|
{
|
|
"EventName": "ex_ret_near_ret_mispred",
|
|
"EventCode": "0xc9",
|
|
"BriefDescription": "Retired near returns mispredicted. Each misprediction incurs the same penalty as a mispredicted conditional branch instruction."
|
|
},
|
|
{
|
|
"EventName": "ex_ret_brn_ind_misp",
|
|
"EventCode": "0xca",
|
|
"BriefDescription": "Retired indirect branch instructions mispredicted (only EX mispredicts). Each misprediction incurs the same penalty as a mispredicted conditional branch instruction."
|
|
},
|
|
{
|
|
"EventName": "ex_ret_ind_brch_instr",
|
|
"EventCode": "0xcc",
|
|
"BriefDescription": "Retired indirect branch instructions."
|
|
},
|
|
{
|
|
"EventName": "ex_ret_cond",
|
|
"EventCode": "0xd1",
|
|
"BriefDescription": "Retired conditional branch instructions."
|
|
},
|
|
{
|
|
"EventName": "ex_ret_msprd_brnch_instr_dir_msmtch",
|
|
"EventCode": "0x1c7",
|
|
"BriefDescription": "Retired branch instructions mispredicted due to direction mismatch."
|
|
},
|
|
{
|
|
"EventName": "ex_ret_uncond_brnch_instr_mispred",
|
|
"EventCode": "0x1c8",
|
|
"BriefDescription": "Retired unconditional indirect branch instructions mispredicted."
|
|
},
|
|
{
|
|
"EventName": "ex_ret_uncond_brnch_instr",
|
|
"EventCode": "0x1c9",
|
|
"BriefDescription": "Retired unconditional branch instructions."
|
|
}
|
|
]
|