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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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8d40f74ebf
There are cases where a metric requires more events than the number of available counters. E.g. AMD Zen, Zen 2 and Zen 3 processors have four data fabric counters but the "nps1_die_to_dram" metric has eight events. By default, the constituent events are placed in a group and since the events cannot be scheduled at the same time, the metric is not computed. The "all metrics" test also fails because of this. Use the NO_GROUP_EVENTS constraint for such metrics which anyway expect the user to run perf with "--metric-no-group". E.g. $ sudo perf test -v 101 Before: 101: perf all metrics test : --- start --- test child forked, pid 37131 Testing branch_misprediction_ratio Testing all_remote_links_outbound Testing nps1_die_to_dram Metric 'nps1_die_to_dram' not printed in: Error: Invalid event (dram_channel_data_controller_4) in per-thread mode, enable system wide with '-a'. Testing macro_ops_dispatched Testing all_l2_cache_accesses Testing all_l2_cache_hits Testing all_l2_cache_misses Testing ic_fetch_miss_ratio Testing l2_cache_accesses_from_l2_hwpf Testing l2_cache_misses_from_l2_hwpf Testing op_cache_fetch_miss_ratio Testing l3_read_miss_latency Testing l1_itlb_misses test child finished with -1 ---- end ---- perf all metrics test: FAILED! After: 101: perf all metrics test : --- start --- test child forked, pid 43766 Testing branch_misprediction_ratio Testing all_remote_links_outbound Testing nps1_die_to_dram Testing macro_ops_dispatched Testing all_l2_cache_accesses Testing all_l2_cache_hits Testing all_l2_cache_misses Testing ic_fetch_miss_ratio Testing l2_cache_accesses_from_l2_hwpf Testing l2_cache_misses_from_l2_hwpf Testing op_cache_fetch_miss_ratio Testing l3_read_miss_latency Testing l1_itlb_misses test child finished with 0 ---- end ---- perf all metrics test: Ok Reported-by: Ayush Jain <ayush.jain3@amd.com> Suggested-by: Ian Rogers <irogers@google.com> Signed-off-by: Sandipan Das <sandipan.das@amd.com> Acked-by: Ian Rogers <irogers@google.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ananth Narayan <ananth.narayan@amd.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ravi Bangoria <ravi.bangoria@amd.com> Cc: Santosh Shukla <santosh.shukla@amd.com> Link: https://lore.kernel.org/r/20230706063440.54189-1-sandipan.das@amd.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
180 lines
5.6 KiB
JSON
180 lines
5.6 KiB
JSON
[
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{
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"MetricName": "branch_misprediction_ratio",
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"BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)",
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"MetricExpr": "d_ratio(ex_ret_brn_misp, ex_ret_brn)",
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"MetricGroup": "branch_prediction",
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"ScaleUnit": "100%"
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},
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{
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"EventName": "all_dc_accesses",
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"EventCode": "0x29",
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"BriefDescription": "All L1 Data Cache Accesses",
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"UMask": "0x07"
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},
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{
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"MetricName": "all_l2_cache_accesses",
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"BriefDescription": "All L2 Cache Accesses",
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"MetricExpr": "l2_request_g1.all_no_prefetch + l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
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"MetricGroup": "l2_cache"
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},
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{
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"EventName": "l2_cache_accesses_from_ic_misses",
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"EventCode": "0x60",
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"BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
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"UMask": "0x10"
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},
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{
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"EventName": "l2_cache_accesses_from_dc_misses",
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"EventCode": "0x60",
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"BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
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"UMask": "0xc8"
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},
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{
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"MetricName": "l2_cache_accesses_from_l2_hwpf",
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"BriefDescription": "L2 Cache Accesses from L2 HWPF",
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"MetricExpr": "l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
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"MetricGroup": "l2_cache"
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},
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{
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"MetricName": "all_l2_cache_misses",
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"BriefDescription": "All L2 Cache Misses",
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"MetricExpr": "l2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
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"MetricGroup": "l2_cache"
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},
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{
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"EventName": "l2_cache_misses_from_ic_miss",
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"EventCode": "0x64",
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"BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
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"UMask": "0x01"
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},
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{
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"EventName": "l2_cache_misses_from_dc_misses",
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"EventCode": "0x64",
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"BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
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"UMask": "0x08"
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},
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{
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"MetricName": "l2_cache_misses_from_l2_hwpf",
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"BriefDescription": "L2 Cache Misses from L2 HWPF",
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"MetricExpr": "l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
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"MetricGroup": "l2_cache"
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},
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{
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"MetricName": "all_l2_cache_hits",
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"BriefDescription": "All L2 Cache Hits",
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"MetricExpr": "l2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2",
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"MetricGroup": "l2_cache"
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},
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{
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"EventName": "l2_cache_hits_from_ic_misses",
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"EventCode": "0x64",
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"BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
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"UMask": "0x06"
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},
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{
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"EventName": "l2_cache_hits_from_dc_misses",
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"EventCode": "0x64",
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"BriefDescription": "L2 Cache Hits from L1 Data Cache Misses",
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"UMask": "0x70"
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},
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{
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"EventName": "l2_cache_hits_from_l2_hwpf",
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"EventCode": "0x70",
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"BriefDescription": "L2 Cache Hits from L2 HWPF",
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"UMask": "0xff"
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},
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{
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"EventName": "l3_accesses",
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"EventCode": "0x04",
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"BriefDescription": "L3 Accesses",
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"UMask": "0xff",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_misses",
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"EventCode": "0x04",
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"BriefDescription": "L3 Misses (includes Chg2X)",
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"UMask": "0x01",
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"Unit": "L3PMC"
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},
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{
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"MetricName": "l3_read_miss_latency",
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"BriefDescription": "Average L3 Read Miss Latency (in core clocks)",
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"MetricExpr": "(xi_sys_fill_latency * 16) / xi_ccx_sdp_req1.all_l3_miss_req_typs",
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"MetricGroup": "l3_cache",
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"ScaleUnit": "1core clocks"
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},
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{
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"MetricName": "ic_fetch_miss_ratio",
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"BriefDescription": "L1 Instruction Cache (32B) Fetch Miss Ratio",
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"MetricExpr": "d_ratio(l2_cache_req_stat.ic_access_in_l2, bp_l1_tlb_fetch_hit + bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_tlb_miss)",
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"MetricGroup": "l2_cache",
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"ScaleUnit": "100%"
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},
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{
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"MetricName": "l1_itlb_misses",
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"BriefDescription": "L1 ITLB Misses",
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"MetricExpr": "bp_l1_tlb_miss_l2_hit + bp_l1_tlb_miss_l2_tlb_miss",
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"MetricGroup": "tlb"
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},
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{
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"EventName": "l2_itlb_misses",
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"EventCode": "0x85",
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"BriefDescription": "L2 ITLB Misses & Instruction page walks",
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"UMask": "0x07"
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},
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{
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"EventName": "l1_dtlb_misses",
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"EventCode": "0x45",
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"BriefDescription": "L1 DTLB Misses",
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"UMask": "0xff"
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},
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{
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"EventName": "l2_dtlb_misses",
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"EventCode": "0x45",
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"BriefDescription": "L2 DTLB Misses & Data page walks",
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"UMask": "0xf0"
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},
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{
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"EventName": "all_tlbs_flushed",
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"EventCode": "0x78",
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"BriefDescription": "All TLBs Flushed",
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"UMask": "0xdf"
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},
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{
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"EventName": "uops_dispatched",
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"EventCode": "0xaa",
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"BriefDescription": "Micro-ops Dispatched",
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"UMask": "0x03"
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},
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{
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"EventName": "sse_avx_stalls",
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"EventCode": "0x0e",
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"BriefDescription": "Mixed SSE/AVX Stalls",
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"UMask": "0x0e"
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},
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{
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"EventName": "uops_retired",
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"EventCode": "0xc1",
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"BriefDescription": "Micro-ops Retired"
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},
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{
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"MetricName": "all_remote_links_outbound",
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"BriefDescription": "Approximate: Outbound data bytes for all Remote Links for a node (die)",
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"MetricExpr": "remote_outbound_data_controller_0 + remote_outbound_data_controller_1 + remote_outbound_data_controller_2 + remote_outbound_data_controller_3",
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"MetricGroup": "data_fabric",
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"PerPkg": "1",
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"ScaleUnit": "3e-5MiB"
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},
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{
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"MetricName": "nps1_die_to_dram",
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"BriefDescription": "Approximate: Combined DRAM B/bytes of all channels on a NPS1 node (die)",
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"MetricExpr": "dram_channel_data_controller_0 + dram_channel_data_controller_1 + dram_channel_data_controller_2 + dram_channel_data_controller_3 + dram_channel_data_controller_4 + dram_channel_data_controller_5 + dram_channel_data_controller_6 + dram_channel_data_controller_7",
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"MetricConstraint": "NO_GROUP_EVENTS",
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"MetricGroup": "data_fabric",
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"PerPkg": "1",
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"ScaleUnit": "6.1e-5MiB"
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}
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]
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