mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-01 23:46:45 +00:00
4ab1fef5dc
Update events from v1.28 to v1.29. Update event topics, addition of PDIST counter into descriptions, metrics to be generated from the TMA spreadsheet and other small clean ups. Signed-off-by: Ian Rogers <irogers@google.com> Tested-by: Thomas Falcon <thomas.falcon@intel.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Andreas Färber <afaerber@suse.de> Cc: Caleb Biggers <caleb.biggers@intel.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Perry Taylor <perry.taylor@intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Weilin Wang <weilin.wang@intel.com> Link: https://lore.kernel.org/r/20250328175006.43110-3-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
170 lines
8.4 KiB
JSON
170 lines
8.4 KiB
JSON
[
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{
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"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.",
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"Counter": "0,1,2,3,4,5",
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"EventCode": "0x05",
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"EventName": "LD_HEAD.ANY_AT_RET",
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"SampleAfterValue": "1000003",
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"UMask": "0xff"
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},
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{
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"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.",
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"Counter": "0,1,2,3,4,5",
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"EventCode": "0x05",
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"EventName": "LD_HEAD.L1_BOUND_AT_RET",
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"SampleAfterValue": "1000003",
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"UMask": "0xf4"
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},
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{
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"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss.",
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"Counter": "0,1,2,3,4,5",
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"EventCode": "0x05",
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"EventName": "LD_HEAD.L1_MISS_AT_RET",
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"SampleAfterValue": "1000003",
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"UMask": "0x81"
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},
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{
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"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases.",
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"Counter": "0,1,2,3,4,5",
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"EventCode": "0x05",
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"EventName": "LD_HEAD.OTHER_AT_RET",
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"PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases such as pipeline conflicts, fences, etc.",
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"SampleAfterValue": "1000003",
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"UMask": "0xc0"
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},
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{
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"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk.",
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"Counter": "0,1,2,3,4,5",
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"EventCode": "0x05",
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"EventName": "LD_HEAD.PGWALK_AT_RET",
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"SampleAfterValue": "1000003",
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"UMask": "0xa0"
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},
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{
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"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match.",
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"Counter": "0,1,2,3,4,5",
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"EventCode": "0x05",
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"EventName": "LD_HEAD.ST_ADDR_AT_RET",
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"SampleAfterValue": "1000003",
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"UMask": "0x84"
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},
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{
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"BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.",
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"Counter": "0,1,2,3,4,5",
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"EventCode": "0xc3",
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"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
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"SampleAfterValue": "20003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
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"Counter": "0,1,2,3,4,5",
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"EventCode": "0xB7",
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"EventName": "OCR.DEMAND_CODE_RD.DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x784000004",
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"PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM. Available PDIST counters: 0",
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"SampleAfterValue": "100003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.",
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"Counter": "0,1,2,3,4,5",
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"EventCode": "0xB7",
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"EventName": "OCR.DEMAND_CODE_RD.L3_MISS",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x3F84400004",
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"PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache. Available PDIST counters: 0",
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"SampleAfterValue": "100003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts demand data reads that were supplied by DRAM.",
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"Counter": "0,1,2,3,4,5",
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"EventCode": "0xB7",
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"EventName": "OCR.DEMAND_DATA_RD.DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x784000001",
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"PublicDescription": "Counts demand data reads that were supplied by DRAM. Available PDIST counters: 0",
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"SampleAfterValue": "100003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.",
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"Counter": "0,1,2,3,4,5",
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"EventCode": "0xB7",
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"EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x3F84400001",
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"PublicDescription": "Counts demand data reads that were not supplied by the L3 cache. Available PDIST counters: 0",
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"SampleAfterValue": "100003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts demand data reads that were not supplied by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS]",
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"Counter": "0,1,2,3,4,5",
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"EventCode": "0xB7",
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"EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x3F84400001",
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"PublicDescription": "Counts demand data reads that were not supplied by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS] Available PDIST counters: 0",
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"SampleAfterValue": "100003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.",
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"Counter": "0,1,2,3,4,5",
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"EventCode": "0xB7",
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"EventName": "OCR.DEMAND_RFO.DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x784000002",
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"PublicDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM. Available PDIST counters: 0",
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"SampleAfterValue": "100003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
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"Counter": "0,1,2,3,4,5",
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"EventCode": "0xB7",
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"EventName": "OCR.DEMAND_RFO.L3_MISS",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x3F84400002",
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"PublicDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. Available PDIST counters: 0",
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"SampleAfterValue": "100003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS]",
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"Counter": "0,1,2,3,4,5",
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"EventCode": "0xB7",
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"EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x3F84400002",
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"PublicDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS] Available PDIST counters: 0",
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"SampleAfterValue": "100003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts L1 data cache software prefetches which include T0/T1/T2 and NTA (except PREFETCHW) that were supplied by DRAM.",
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"Counter": "0,1,2,3,4,5",
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"EventCode": "0xB7",
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"EventName": "OCR.SWPF_RD.DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x784004000",
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"PublicDescription": "Counts L1 data cache software prefetches which include T0/T1/T2 and NTA (except PREFETCHW) that were supplied by DRAM. Available PDIST counters: 0",
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"SampleAfterValue": "100003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts L1 data cache software prefetches which include T0/T1/T2 and NTA (except PREFETCHW) that were not supplied by the L3 cache.",
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"Counter": "0,1,2,3,4,5",
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"EventCode": "0xB7",
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"EventName": "OCR.SWPF_RD.L3_MISS",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x3F84404000",
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"PublicDescription": "Counts L1 data cache software prefetches which include T0/T1/T2 and NTA (except PREFETCHW) that were not supplied by the L3 cache. Available PDIST counters: 0",
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"SampleAfterValue": "100003",
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"UMask": "0x1"
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}
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]
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