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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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72da747ddd
Update events from v1.24 to v1.27. Update e-core TMA metrics to v3.6. Bring in the event updates v1.27:ea4f309a04v1.26:0052e68d24The e-core TMA 3.6 information was updated in:d9c2faa70bNew events are: MEM_UOPS_RETIRED.LOCK_LOADS, SERIALIZATION.C01_MS_SCB, UOPS_ISSUED.ANY. Co-authored-by: Weilin Wang <weilin.wang@intel.com> Co-authored-by: Caleb Biggers <caleb.biggers@intel.com> Signed-off-by: Ian Rogers <irogers@google.com> Reviewed-by: Kan Liang <kan.liang@linux.intel.com> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Signed-off-by: Namhyung Kim <namhyung@kernel.org> Link: https://lore.kernel.org/r/20240620181752.3945845-3-irogers@google.com
30 lines
2.1 KiB
JSON
30 lines
2.1 KiB
JSON
[
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{
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"BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
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"Counter": "0,1,2,3,4,5",
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"EventCode": "0xe6",
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"EventName": "BACLEARS.ANY",
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"PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
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"SampleAfterValue": "100003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts the number of requests to the instruction cache for one or more bytes of a cache line.",
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"Counter": "0,1,2,3,4,5",
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"EventCode": "0x80",
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"EventName": "ICACHE.ACCESSES",
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"PublicDescription": "Counts the total number of requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line or byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",
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"SampleAfterValue": "200003",
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"UMask": "0x3"
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},
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{
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"BriefDescription": "Counts the number of instruction cache misses.",
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"Counter": "0,1,2,3,4,5",
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"EventCode": "0x80",
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"EventName": "ICACHE.MISSES",
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"PublicDescription": "Counts the number of missed requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.",
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"SampleAfterValue": "200003",
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"UMask": "0x2"
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}
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]
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