mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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dfeab63acd
Update IBM z196/z114 event counter description to the latest level
as described in the documents
1. SA23-2260-07:
"The Load-Program-Parameter and the CPU-Measurement Facilities."
released on May, 2022
for the following counter sets:
* Basic counter set
* Problem counter set
* Crypto counter set
2. SA23-2261-07:
"The CPU-Measurement Facility Extended Counters Definition
for z10, z196/z114, zEC12/zBC12, z13/z13s, z14, z15 and z16"
released on April 29, 2022
for the following counter sets:
* Extended counter set
* MT-Diagnostic counter set
Signed-off-by: Thomas Richter <tmricht@linux.ibm.com>
Acked-by: Sumanth Korikkar <sumanthk@linux.ibm.com>
Acked-by: Ian Rogers <irogers@google.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Link: https://lore.kernel.org/r/20220531092706.1931503-6-tmricht@linux.ibm.com
Cc: acme@kernel.org
Cc: gor@linux.ibm.com
Cc: hca@linux.ibm.com
Cc: svens@linux.ibm.com
Cc: linux-kernel@vger.kernel.org
Cc: linux-perf-users@vger.kernel.org
171 lines
6.9 KiB
JSON
171 lines
6.9 KiB
JSON
[
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{
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"Unit": "CPU-M-CF",
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"EventCode": "128",
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"EventName": "L1D_L2_SOURCED_WRITES",
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"BriefDescription": "L1D L2 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourced from the Level-2 cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "129",
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"EventName": "L1I_L2_SOURCED_WRITES",
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"BriefDescription": "L1I L2 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was sourced from the Level-2 cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "130",
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"EventName": "DTLB1_MISSES",
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"BriefDescription": "DTLB1 Misses",
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"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB1 miss is in progress."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "131",
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"EventName": "ITLB1_MISSES",
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"BriefDescription": "ITLB1 Misses",
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"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle a ITLB1 miss is in progress."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "133",
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"EventName": "L2C_STORES_SENT",
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"BriefDescription": "L2C Stores Sent",
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"PublicDescription": "Incremented by one for every store sent to Level-2 cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "134",
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"EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES",
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"BriefDescription": "L1D Off-Book L3 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourced from an Off Book Level-3 cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "135",
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"EventName": "L1D_ONBOOK_L4_SOURCED_WRITES",
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"BriefDescription": "L1D On-Book L4 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourced from an On Book Level-4 cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "136",
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"EventName": "L1I_ONBOOK_L4_SOURCED_WRITES",
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"BriefDescription": "L1I On-Book L4 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was sourced from an On Book Level-4 cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "137",
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"EventName": "L1D_RO_EXCL_WRITES",
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"BriefDescription": "L1D Read-only Exclusive Writes",
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"PublicDescription": "A directory write to the Level-1 Data Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "138",
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"EventName": "L1D_OFFBOOK_L4_SOURCED_WRITES",
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"BriefDescription": "L1D Off-Book L4 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourced from an Off Book Level-4 cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "139",
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"EventName": "L1I_OFFBOOK_L4_SOURCED_WRITES",
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"BriefDescription": "L1I Off-Book L4 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was sourced from an Off Book Level-4 cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "140",
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"EventName": "DTLB1_HPAGE_WRITES",
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"BriefDescription": "DTLB1 One-Megabyte Page Writes",
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"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "141",
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"EventName": "L1D_LMEM_SOURCED_WRITES",
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"BriefDescription": "L1D Local Memory Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Data Cache where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "142",
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"EventName": "L1I_LMEM_SOURCED_WRITES",
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"BriefDescription": "L1I Local Memory Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Instruction Cache where the installed cache line was sourced from memory that is attached to the same book as the Instruction cache (Local Memory)."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "143",
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"EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES",
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"BriefDescription": "L1I Off-Book L3 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was sourced from an Off Book Level-3 cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "144",
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"EventName": "DTLB1_WRITES",
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"BriefDescription": "DTLB1 Writes",
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"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer (DTLB1)."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "145",
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"EventName": "ITLB1_WRITES",
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"BriefDescription": "ITLB1 Writes",
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"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer (ITLB1)."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "146",
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"EventName": "TLB2_PTE_WRITES",
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"BriefDescription": "TLB2 PTE Writes",
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"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "147",
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"EventName": "TLB2_CRSTE_HPAGE_WRITES",
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"BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
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"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "148",
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"EventName": "TLB2_CRSTE_WRITES",
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"BriefDescription": "TLB2 CRSTE Writes",
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"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "150",
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"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES",
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"BriefDescription": "L1D On-Chip L3 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourced from an On Chip Level-3 cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "152",
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"EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES",
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"BriefDescription": "L1D Off-Chip L3 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "153",
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"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES",
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"BriefDescription": "L1I On-Chip L3 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was sourced from an On Chip Level-3 cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "155",
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"EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES",
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"BriefDescription": "L1I Off-Chip L3 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache."
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}
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]
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