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508b228942
Update IBM z17 counter description using document SA23-2260-08: "The Load-Program-Parameter and the CPU-Measurement Facilities" released in May 2025 to include counter definitions for IBM z17 counter sets: * Basic counter set * Problem/user counter set * Crypto counter set. Use document SA23-2261-09: "The CPU-Measurement Facility Extended Counters Definition for z10, z196/z114, zEC12/zBC12, z13/z13s, z14, z15, z16 and z17" released on April 2025 to include counter definitions for IBM z17 * Extended counter set * MT-Diagnostic counter set. Use document SA22-7832-14: "z/Architecture Principles of Operation." released in April 2025 to include counter definitions for IBM z17 * PAI-Crypto counter set * PAI-Extention counter set. Use document "CPU MF Formulas and Updates April 2025" released in April 2025 to include metric calculations. Signed-off-by: Thomas Richter <tmricht@linux.ibm.com> Acked-by: Sumanth Korikkar <sumanthk@linux.ibm.com> Reviewed-by: Ian Rogers <irogers@google.com> Link: https://lore.kernel.org/r/20250623132731.899525-1-tmricht@linux.ibm.com Signed-off-by: Namhyung Kim <namhyung@kernel.org>
73 lines
3.7 KiB
JSON
73 lines
3.7 KiB
JSON
[
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{
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"BriefDescription": "Transaction count",
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"MetricName": "transaction",
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"MetricExpr": "TX_C_TEND + TX_NC_TEND + TX_NC_TABORT + TX_C_TABORT_SPECIAL + TX_C_TABORT_NO_SPECIAL if has_event(TX_C_TEND) else 0"
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},
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{
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"BriefDescription": "Cycles per Instruction",
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"MetricName": "cpi",
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"MetricExpr": "CPU_CYCLES / INSTRUCTIONS if has_event(INSTRUCTIONS) else 0"
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},
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{
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"BriefDescription": "Problem State Instruction Ratio",
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"MetricName": "prbstate",
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"MetricExpr": "(PROBLEM_STATE_INSTRUCTIONS / INSTRUCTIONS) * 100 if has_event(INSTRUCTIONS) else 0"
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},
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{
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"BriefDescription": "Level One Miss per 100 Instructions",
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"MetricName": "l1mp",
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"MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100 if has_event(INSTRUCTIONS) else 0"
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},
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{
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"BriefDescription": "Percentage sourced from Level 2 cache",
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"MetricName": "l2p",
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"MetricExpr": "((DCW_REQ + DCW_REQ_IV + ICW_REQ + ICW_REQ_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_REQ) else 0"
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},
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{
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"BriefDescription": "Percentage sourced from Level 3 on same chip cache",
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"MetricName": "l3p",
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"MetricExpr": "((DCW_REQ_CHIP_HIT + DCW_ON_CHIP + DCW_ON_CHIP_IV + DCW_ON_CHIP_CHIP_HIT + ICW_REQ_CHIP_HIT + ICW_ON_CHIP + ICW_ON_CHIP_IV + ICW_ON_CHIP_CHIP_HIT) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_REQ_CHIP_HIT) else 0"
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},
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{
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"BriefDescription": "Percentage sourced from Level 4 Local cache on same drawer",
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"MetricName": "l4lp",
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"MetricExpr": "((DCW_REQ_DRAWER_HIT + DCW_ON_CHIP_DRAWER_HIT + DCW_ON_MODULE + DCW_ON_DRAWER + IDCW_ON_MODULE_IV + IDCW_ON_MODULE_CHIP_HIT + IDCW_ON_MODULE_DRAWER_HIT + IDCW_ON_DRAWER_IV + IDCW_ON_DRAWER_CHIP_HIT + IDCW_ON_DRAWER_DRAWER_HIT + ICW_REQ_DRAWER_HIT + ICW_ON_CHIP_DRAWER_HIT + ICW_ON_MODULE + ICW_ON_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_REQ_DRAWER_HIT) else 0"
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},
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{
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"BriefDescription": "Percentage sourced from Level 4 Remote cache on different book",
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"MetricName": "l4rp",
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"MetricExpr": "((DCW_OFF_DRAWER + IDCW_OFF_DRAWER_IV + IDCW_OFF_DRAWER_CHIP_HIT + IDCW_OFF_DRAWER_DRAWER_HIT + ICW_OFF_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_OFF_DRAWER) else 0"
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},
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{
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"BriefDescription": "Percentage sourced from memory",
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"MetricName": "memp",
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"MetricExpr": "((DCW_ON_CHIP_MEMORY + DCW_ON_MODULE_MEMORY + DCW_ON_DRAWER_MEMORY + DCW_OFF_DRAWER_MEMORY) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100 if has_event(DCW_ON_CHIP_MEMORY) else 0"
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},
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{
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"BriefDescription": "Cycles per Instructions from Finite cache/memory",
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"MetricName": "finite_cpi",
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"MetricExpr": "L1C_TLB2_MISSES / INSTRUCTIONS if has_event(L1C_TLB2_MISSES) else 0"
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},
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{
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"BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1",
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"MetricName": "est_cpi",
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"MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS) if has_event(INSTRUCTIONS) else 0"
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},
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{
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"BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss",
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"MetricName": "scpl1m",
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"MetricExpr": "L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES) if has_event(L1C_TLB2_MISSES) else 0"
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},
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{
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"BriefDescription": "Estimated TLB CPU percentage of Total CPU",
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"MetricName": "tlb_percent",
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"MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100 if has_event(CPU_CYCLES) else 0"
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},
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{
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"BriefDescription": "Estimated Cycles per TLB Miss",
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"MetricName": "tlb_miss",
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"MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) if has_event(DTLB2_MISSES) else 0"
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}
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]
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