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508b228942
Update IBM z17 counter description using document SA23-2260-08: "The Load-Program-Parameter and the CPU-Measurement Facilities" released in May 2025 to include counter definitions for IBM z17 counter sets: * Basic counter set * Problem/user counter set * Crypto counter set. Use document SA23-2261-09: "The CPU-Measurement Facility Extended Counters Definition for z10, z196/z114, zEC12/zBC12, z13/z13s, z14, z15, z16 and z17" released on April 2025 to include counter definitions for IBM z17 * Extended counter set * MT-Diagnostic counter set. Use document SA22-7832-14: "z/Architecture Principles of Operation." released in April 2025 to include counter definitions for IBM z17 * PAI-Crypto counter set * PAI-Extention counter set. Use document "CPU MF Formulas and Updates April 2025" released in April 2025 to include metric calculations. Signed-off-by: Thomas Richter <tmricht@linux.ibm.com> Acked-by: Sumanth Korikkar <sumanthk@linux.ibm.com> Reviewed-by: Ian Rogers <irogers@google.com> Link: https://lore.kernel.org/r/20250623132731.899525-1-tmricht@linux.ibm.com Signed-off-by: Namhyung Kim <namhyung@kernel.org>
59 lines
2.1 KiB
JSON
59 lines
2.1 KiB
JSON
[
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{
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"Unit": "CPU-M-CF",
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"EventCode": "0",
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"EventName": "CPU_CYCLES",
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"BriefDescription": "Cycle Count",
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"PublicDescription": "This counter counts the total number of CPU cycles, excluding the number of cycles while the CPU is in the wait state."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "1",
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"EventName": "INSTRUCTIONS",
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"BriefDescription": "Instruction Count",
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"PublicDescription": "This counter counts the total number of instructions executed by the CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "2",
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"EventName": "L1I_DIR_WRITES",
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"BriefDescription": "Level-1 I-Cache Directory Write Count",
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"PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "3",
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"EventName": "L1I_PENALTY_CYCLES",
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"BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
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"PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 instruction cache or unified cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "4",
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"EventName": "L1D_DIR_WRITES",
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"BriefDescription": "Level-1 D-Cache Directory Write Count",
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"PublicDescription": "This counter counts the total number of level-1 data-cache directory writes."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "5",
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"EventName": "L1D_PENALTY_CYCLES",
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"BriefDescription": "Level-1 D-Cache Penalty Cycle Count",
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"PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 data cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "32",
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"EventName": "PROBLEM_STATE_CPU_CYCLES",
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"BriefDescription": "Problem-State Cycle Count",
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"PublicDescription": "This counter counts the total number of CPU cycles when the CPU is in the problem state, excluding the number of cycles while the CPU is in the wait state."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "33",
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"EventName": "PROBLEM_STATE_INSTRUCTIONS",
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"BriefDescription": "Problem-State Instruction Count",
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"PublicDescription": "This counter counts the total number of instructions executed by the CPU while in the problem state."
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}
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]
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