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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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0edee81971
Move some of the JSON/events from others.json to more appropriate JSON files for power10 platform. Reviewed-by: Ian Rogers <irogers@google.com> Signed-off-by: Kajol Jain <kjain@linux.ibm.com> Cc: Athira Rajeev <atrajeev@linux.vnet.ibm.com> Cc: Disha Goel <disgoel@linux.vnet.ibm.com> Cc: Hari Bathini <hbathini@linux.ibm.com> Cc: Ian Rogers <irogers@google.com> Cc: Madhavan Srinivasan <maddy@linux.ibm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: linuxppc-dev@lists.ozlabs.org Link: https://lore.kernel.org/r/20240827053206.538814-2-kjain@linux.ibm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
143 lines
7.0 KiB
JSON
143 lines
7.0 KiB
JSON
[
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{
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"EventCode": "0x1C040",
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"EventName": "PM_XFER_FROM_SRC_PMC1",
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"BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[0:12]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
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},
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{
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"EventCode": "0x1C056",
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"EventName": "PM_DERAT_MISS_4K",
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"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
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},
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{
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"EventCode": "0x1C058",
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"EventName": "PM_DTLB_MISS_16G",
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"BriefDescription": "Data TLB reload (after a miss) page size 16G. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
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},
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{
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"EventCode": "0x1C05C",
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"EventName": "PM_DTLB_MISS_2M",
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"BriefDescription": "Data TLB reload (after a miss) page size 2M. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
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},
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{
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"EventCode": "0x10062",
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"EventName": "PM_LD_L3MISS_PEND_CYC",
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"BriefDescription": "Cycles in which an L3 miss was pending for this thread."
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},
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{
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"EventCode": "0x2001A",
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"EventName": "PM_ITLB_HIT",
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"BriefDescription": "The PTE required to translate the instruction address was resident in the TLB (instruction TLB access/IERAT reload). Applies to both HPT and RPT. When MMCR1[17]=0 this event counts only for demand misses. When MMCR1[17]=1 this event includes demand misses and prefetches."
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},
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{
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"EventCode": "0x2003E",
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"EventName": "PM_PTESYNC_FIN",
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"BriefDescription": "Ptesync instruction finished in the store unit. Only one ptesync can finish at a time."
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},
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{
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"EventCode": "0x2C040",
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"EventName": "PM_XFER_FROM_SRC_PMC2",
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"BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[15:27]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
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},
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{
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"EventCode": "0x2C054",
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"EventName": "PM_DERAT_MISS_64K",
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"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
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},
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{
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"EventCode": "0x2C056",
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"EventName": "PM_DTLB_MISS_4K",
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"BriefDescription": "Data TLB reload (after a miss) page size 4K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
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},
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{
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"EventCode": "0x2C05A",
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"EventName": "PM_DERAT_MISS_1G",
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"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 1G. Implies radix translation. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
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},
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{
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"EventCode": "0x200F6",
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"EventName": "PM_DERAT_MISS",
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"BriefDescription": "DERAT Reloaded to satisfy a DERAT miss. All page sizes are counted by this event. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
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},
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{
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"EventCode": "0x34044",
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"EventName": "PM_DERAT_MISS_PREF",
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"BriefDescription": "DERAT miss (TLB access) while servicing a data prefetch."
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},
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{
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"EventCode": "0x3C040",
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"EventName": "PM_XFER_FROM_SRC_PMC3",
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"BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[30:42]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
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},
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{
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"EventCode": "0x3F04A",
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"EventName": "PM_LSU_ST5_FIN",
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"BriefDescription": "LSU Finished an internal operation in ST2 port."
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},
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{
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"EventCode": "0x3C054",
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"EventName": "PM_DERAT_MISS_16M",
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"BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M. When MMCR1[16]=0 this event counts only DERAT reloads for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
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},
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{
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"EventCode": "0x3C056",
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"EventName": "PM_DTLB_MISS_64K",
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"BriefDescription": "Data TLB reload (after a miss) page size 64K. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
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},
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{
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"EventCode": "0x3C058",
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"EventName": "PM_LARX_FIN",
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"BriefDescription": "Load and reserve instruction (LARX) finished. LARX and STCX are instructions used to acquire a lock."
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},
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{
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"EventCode": "0x300FC",
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"EventName": "PM_DTLB_MISS",
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"BriefDescription": "The DPTEG required for the load/store instruction in execution was missing from the TLB. This event only counts for demand misses."
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},
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{
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"EventCode": "0x4003E",
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"EventName": "PM_LD_CMPL",
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"BriefDescription": "Load instruction completed."
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},
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{
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"EventCode": "0x4C040",
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"EventName": "PM_XFER_FROM_SRC_PMC4",
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"BriefDescription": "The processor's L1 data cache was reloaded from the source specified in MMCR3[45:57]. If MMCR1[16|17] is 0 (default), this count includes only lines that were reloaded to satisfy a demand miss. If MMCR1[16|17] is 1, this count includes both demand misses and prefetch reloads."
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},
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{
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"EventCode": "0x4C056",
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"EventName": "PM_DTLB_MISS_16M",
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"BriefDescription": "Data TLB reload (after a miss) page size 16M. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
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},
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{
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"EventCode": "0x4C05A",
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"EventName": "PM_DTLB_MISS_1G",
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"BriefDescription": "Data TLB reload (after a miss) page size 1G. Implies radix translation was used. When MMCR1[16]=0 this event counts only for demand misses. When MMCR1[16]=1 this event includes demand misses and prefetches."
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},
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{
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"EventCode": "0x000000F880",
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"EventName": "PM_SNOOP_TLBIE_CYC",
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"BriefDescription": "Cycles in which TLBIE snoops are executed in the LSU."
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},
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{
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"EventCode": "0x000000F084",
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"EventName": "PM_SNOOP_TLBIE_CACHE_WALK_CYC",
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"BriefDescription": "TLBIE snoop cycles in which the data cache is being walked."
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},
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{
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"EventCode": "0x000000F884",
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"EventName": "PM_SNOOP_TLBIE_WAIT_ST_CYC",
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"BriefDescription": "TLBIE snoop cycles in which older stores are still draining."
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},
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{
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"EventCode": "0x000000F088",
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"EventName": "PM_SNOOP_TLBIE_WAIT_LD_CYC",
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"BriefDescription": "TLBIE snoop cycles in which older loads are still draining."
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},
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{
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"EventCode": "0x000000F08C",
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"EventName": "PM_SNOOP_TLBIE_WAIT_MMU_CYC",
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"BriefDescription": "TLBIE snoop cycles in which the Load-Store unit is waiting for the MMU to finish invalidation."
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}
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]
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