mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-02 16:44:59 +00:00
7269846617
Update using the new data [1] for these changes:
* Scale some metrics like dtlb_walk_ratio to percent so they display
better with Perf's 2 dp precision
* Description typos, grammar and clarifications
* Unnecessary metric formula brackets seem to have been removed in the
source but this is not a functional change
* New sve_all_percentage metric
The following command was used to generate this commit:
$ telemetry-solution/tools/perf_json_generator/generate.py \
tools/perf/ --telemetry-files \
telemetry-solution/data/pmu/cpu/neoverse/neoverse-v2.json:neoverse-n2-v2
[1]: https://gitlab.arm.com/telemetry-solution/telemetry-solution/-/blob/main/data/pmu/cpu/neoverse/neoverse-v2.json
Reviewed-by: Ian Rogers <irogers@google.com>
Signed-off-by: James Clark <james.clark@linaro.org>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Leo Yan <leo.yan@linux.dev>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lore.kernel.org/r/20241120143739.243728-1-james.clark@linaro.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
312 lines
16 KiB
JSON
312 lines
16 KiB
JSON
[
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{
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"ArchStdEvent": "backend_bound",
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"MetricExpr": "(100 * ((STALL_SLOT_BACKEND / (CPU_CYCLES * #slots)) - ((BR_MIS_PRED * 3) / CPU_CYCLES)))"
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},
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{
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"MetricName": "backend_stalled_cycles",
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"MetricExpr": "STALL_BACKEND / CPU_CYCLES * 100",
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"BriefDescription": "This metric is the percentage of cycles that were stalled due to resource constraints in the backend unit of the processor.",
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"MetricGroup": "Cycle_Accounting",
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"ScaleUnit": "1percent of cycles"
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},
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{
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"ArchStdEvent": "bad_speculation",
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"MetricExpr": "(100 * (((1 - (OP_RETIRED / OP_SPEC)) * (1 - (((STALL_SLOT) if (strcmp_cpuid_str(0x410fd493) | strcmp_cpuid_str(0x410fd490) ^ 1) else (STALL_SLOT - CPU_CYCLES)) / (CPU_CYCLES * #slots)))) + ((BR_MIS_PRED * 4) / CPU_CYCLES)))"
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},
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{
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"MetricName": "branch_misprediction_ratio",
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"MetricExpr": "BR_MIS_PRED_RETIRED / BR_RETIRED",
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"BriefDescription": "This metric measures the ratio of branches mispredicted to the total number of branches architecturally executed. This gives an indication of the effectiveness of the branch prediction unit.",
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"MetricGroup": "Miss_Ratio;Branch_Effectiveness",
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"ScaleUnit": "100percent of branches"
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},
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{
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"MetricName": "branch_mpki",
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"MetricExpr": "BR_MIS_PRED_RETIRED / INST_RETIRED * 1000",
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"BriefDescription": "This metric measures the number of branch mispredictions per thousand instructions executed.",
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"MetricGroup": "MPKI;Branch_Effectiveness",
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"ScaleUnit": "1MPKI"
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},
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{
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"MetricName": "branch_percentage",
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"MetricExpr": "(BR_IMMED_SPEC + BR_INDIRECT_SPEC) / INST_SPEC * 100",
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"BriefDescription": "This metric measures branch operations as a percentage of operations speculatively executed.",
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"MetricGroup": "Operation_Mix",
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"ScaleUnit": "1percent of operations"
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},
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{
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"MetricName": "crypto_percentage",
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"MetricExpr": "CRYPTO_SPEC / INST_SPEC * 100",
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"BriefDescription": "This metric measures crypto operations as a percentage of operations speculatively executed.",
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"MetricGroup": "Operation_Mix",
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"ScaleUnit": "1percent of operations"
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},
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{
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"MetricName": "dtlb_mpki",
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"MetricExpr": "DTLB_WALK / INST_RETIRED * 1000",
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"BriefDescription": "This metric measures the number of data TLB Walks per thousand instructions executed.",
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"MetricGroup": "MPKI;DTLB_Effectiveness",
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"ScaleUnit": "1MPKI"
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},
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{
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"MetricName": "dtlb_walk_ratio",
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"MetricExpr": "DTLB_WALK / L1D_TLB",
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"BriefDescription": "This metric measures the ratio of data TLB Walks to the total number of data TLB accesses. This gives an indication of the effectiveness of the data TLB accesses.",
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"MetricGroup": "Miss_Ratio;DTLB_Effectiveness",
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"ScaleUnit": "100percent of TLB accesses"
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},
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{
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"ArchStdEvent": "frontend_bound",
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"MetricExpr": "(100 * ((((STALL_SLOT_FRONTEND) if (strcmp_cpuid_str(0x410fd493) | strcmp_cpuid_str(0x410fd490) ^ 1) else (STALL_SLOT_FRONTEND - CPU_CYCLES)) / (CPU_CYCLES * #slots)) - (BR_MIS_PRED / CPU_CYCLES)))"
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},
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{
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"MetricName": "frontend_stalled_cycles",
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"MetricExpr": "STALL_FRONTEND / CPU_CYCLES * 100",
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"BriefDescription": "This metric is the percentage of cycles that were stalled due to resource constraints in the frontend unit of the processor.",
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"MetricGroup": "Cycle_Accounting",
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"ScaleUnit": "1percent of cycles"
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},
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{
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"MetricName": "integer_dp_percentage",
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"MetricExpr": "DP_SPEC / INST_SPEC * 100",
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"BriefDescription": "This metric measures scalar integer operations as a percentage of operations speculatively executed.",
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"MetricGroup": "Operation_Mix",
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"ScaleUnit": "1percent of operations"
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},
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{
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"MetricName": "ipc",
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"MetricExpr": "INST_RETIRED / CPU_CYCLES",
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"BriefDescription": "This metric measures the number of instructions retired per cycle.",
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"MetricGroup": "General",
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"ScaleUnit": "1per cycle"
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},
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{
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"MetricName": "itlb_mpki",
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"MetricExpr": "ITLB_WALK / INST_RETIRED * 1000",
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"BriefDescription": "This metric measures the number of instruction TLB Walks per thousand instructions executed.",
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"MetricGroup": "MPKI;ITLB_Effectiveness",
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"ScaleUnit": "1MPKI"
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},
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{
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"MetricName": "itlb_walk_ratio",
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"MetricExpr": "ITLB_WALK / L1I_TLB",
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"BriefDescription": "This metric measures the ratio of instruction TLB Walks to the total number of instruction TLB accesses. This gives an indication of the effectiveness of the instruction TLB accesses.",
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"MetricGroup": "Miss_Ratio;ITLB_Effectiveness",
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"ScaleUnit": "100percent of TLB accesses"
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},
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{
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"MetricName": "l1d_cache_miss_ratio",
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"MetricExpr": "L1D_CACHE_REFILL / L1D_CACHE",
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"BriefDescription": "This metric measures the ratio of level 1 data cache accesses missed to the total number of level 1 data cache accesses. This gives an indication of the effectiveness of the level 1 data cache.",
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"MetricGroup": "Miss_Ratio;L1D_Cache_Effectiveness",
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"ScaleUnit": "100percent of cache accesses"
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},
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{
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"MetricName": "l1d_cache_mpki",
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"MetricExpr": "L1D_CACHE_REFILL / INST_RETIRED * 1000",
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"BriefDescription": "This metric measures the number of level 1 data cache accesses missed per thousand instructions executed.",
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"MetricGroup": "MPKI;L1D_Cache_Effectiveness",
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"ScaleUnit": "1MPKI"
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},
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{
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"MetricName": "l1d_tlb_miss_ratio",
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"MetricExpr": "L1D_TLB_REFILL / L1D_TLB",
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"BriefDescription": "This metric measures the ratio of level 1 data TLB accesses missed to the total number of level 1 data TLB accesses. This gives an indication of the effectiveness of the level 1 data TLB.",
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"MetricGroup": "Miss_Ratio;DTLB_Effectiveness",
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"ScaleUnit": "100percent of TLB accesses"
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},
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{
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"MetricName": "l1d_tlb_mpki",
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"MetricExpr": "L1D_TLB_REFILL / INST_RETIRED * 1000",
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"BriefDescription": "This metric measures the number of level 1 data TLB accesses missed per thousand instructions executed.",
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"MetricGroup": "MPKI;DTLB_Effectiveness",
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"ScaleUnit": "1MPKI"
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},
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{
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"MetricName": "l1i_cache_miss_ratio",
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"MetricExpr": "L1I_CACHE_REFILL / L1I_CACHE",
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"BriefDescription": "This metric measures the ratio of level 1 instruction cache accesses missed to the total number of level 1 instruction cache accesses. This gives an indication of the effectiveness of the level 1 instruction cache.",
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"MetricGroup": "Miss_Ratio;L1I_Cache_Effectiveness",
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"ScaleUnit": "100percent of cache accesses"
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},
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{
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"MetricName": "l1i_cache_mpki",
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"MetricExpr": "L1I_CACHE_REFILL / INST_RETIRED * 1000",
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"BriefDescription": "This metric measures the number of level 1 instruction cache accesses missed per thousand instructions executed.",
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"MetricGroup": "MPKI;L1I_Cache_Effectiveness",
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"ScaleUnit": "1MPKI"
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},
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{
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"MetricName": "l1i_tlb_miss_ratio",
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"MetricExpr": "L1I_TLB_REFILL / L1I_TLB",
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"BriefDescription": "This metric measures the ratio of level 1 instruction TLB accesses missed to the total number of level 1 instruction TLB accesses. This gives an indication of the effectiveness of the level 1 instruction TLB.",
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"MetricGroup": "Miss_Ratio;ITLB_Effectiveness",
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"ScaleUnit": "100percent of TLB accesses"
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},
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{
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"MetricName": "l1i_tlb_mpki",
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"MetricExpr": "L1I_TLB_REFILL / INST_RETIRED * 1000",
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"BriefDescription": "This metric measures the number of level 1 instruction TLB accesses missed per thousand instructions executed.",
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"MetricGroup": "MPKI;ITLB_Effectiveness",
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"ScaleUnit": "1MPKI"
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},
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{
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"MetricName": "l2_cache_miss_ratio",
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"MetricExpr": "L2D_CACHE_REFILL / L2D_CACHE",
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"BriefDescription": "This metric measures the ratio of level 2 cache accesses missed to the total number of level 2 cache accesses. This gives an indication of the effectiveness of the level 2 cache, which is a unified cache that stores both data and instruction. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a unified cache.",
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"MetricGroup": "Miss_Ratio;L2_Cache_Effectiveness",
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"ScaleUnit": "100percent of cache accesses"
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},
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{
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"MetricName": "l2_cache_mpki",
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"MetricExpr": "L2D_CACHE_REFILL / INST_RETIRED * 1000",
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"BriefDescription": "This metric measures the number of level 2 unified cache accesses missed per thousand instructions executed. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a unified cache.",
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"MetricGroup": "MPKI;L2_Cache_Effectiveness",
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"ScaleUnit": "1MPKI"
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},
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{
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"MetricName": "l2_tlb_miss_ratio",
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"MetricExpr": "L2D_TLB_REFILL / L2D_TLB",
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"BriefDescription": "This metric measures the ratio of level 2 unified TLB accesses missed to the total number of level 2 unified TLB accesses. This gives an indication of the effectiveness of the level 2 TLB.",
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"MetricGroup": "Miss_Ratio;ITLB_Effectiveness;DTLB_Effectiveness",
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"ScaleUnit": "100percent of TLB accesses"
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},
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{
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"MetricName": "l2_tlb_mpki",
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"MetricExpr": "L2D_TLB_REFILL / INST_RETIRED * 1000",
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"BriefDescription": "This metric measures the number of level 2 unified TLB accesses missed per thousand instructions executed.",
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"MetricGroup": "MPKI;ITLB_Effectiveness;DTLB_Effectiveness",
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"ScaleUnit": "1MPKI"
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},
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{
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"MetricName": "ll_cache_read_hit_ratio",
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"MetricExpr": "(LL_CACHE_RD - LL_CACHE_MISS_RD) / LL_CACHE_RD",
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"BriefDescription": "This metric measures the ratio of last level cache read accesses hit in the cache to the total number of last level cache accesses. This gives an indication of the effectiveness of the last level cache for read traffic. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a system level cache.",
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"MetricGroup": "LL_Cache_Effectiveness",
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"ScaleUnit": "100percent of cache accesses"
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},
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{
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"MetricName": "ll_cache_read_miss_ratio",
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"MetricExpr": "LL_CACHE_MISS_RD / LL_CACHE_RD",
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"BriefDescription": "This metric measures the ratio of last level cache read accesses missed to the total number of last level cache accesses. This gives an indication of the effectiveness of the last level cache for read traffic. Note that cache accesses in this cache are either data memory access or instruction fetch as this is a system level cache.",
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"MetricGroup": "Miss_Ratio;LL_Cache_Effectiveness",
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"ScaleUnit": "100percent of cache accesses"
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},
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{
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"MetricName": "ll_cache_read_mpki",
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"MetricExpr": "LL_CACHE_MISS_RD / INST_RETIRED * 1000",
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"BriefDescription": "This metric measures the number of last level cache read accesses missed per thousand instructions executed.",
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"MetricGroup": "MPKI;LL_Cache_Effectiveness",
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"ScaleUnit": "1MPKI"
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},
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{
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"MetricName": "load_percentage",
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"MetricExpr": "LD_SPEC / INST_SPEC * 100",
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"BriefDescription": "This metric measures load operations as a percentage of operations speculatively executed.",
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"MetricGroup": "Operation_Mix",
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"ScaleUnit": "1percent of operations"
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},
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{
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"ArchStdEvent": "retiring",
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"MetricExpr": "(100 * ((OP_RETIRED / OP_SPEC) * (1 - (((STALL_SLOT) if (strcmp_cpuid_str(0x410fd493) | strcmp_cpuid_str(0x410fd490) ^ 1) else (STALL_SLOT - CPU_CYCLES)) / (CPU_CYCLES * #slots)))))"
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},
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{
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"MetricName": "scalar_fp_percentage",
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"MetricExpr": "VFP_SPEC / INST_SPEC * 100",
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"BriefDescription": "This metric measures scalar floating point operations as a percentage of operations speculatively executed.",
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"MetricGroup": "Operation_Mix",
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"ScaleUnit": "1percent of operations"
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},
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{
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"MetricName": "simd_percentage",
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"MetricExpr": "ASE_SPEC / INST_SPEC * 100",
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"BriefDescription": "This metric measures advanced SIMD operations as a percentage of total operations speculatively executed.",
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"MetricGroup": "Operation_Mix",
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"ScaleUnit": "1percent of operations"
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},
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{
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"MetricName": "store_percentage",
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"MetricExpr": "ST_SPEC / INST_SPEC * 100",
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"BriefDescription": "This metric measures store operations as a percentage of operations speculatively executed.",
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"MetricGroup": "Operation_Mix",
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"ScaleUnit": "1percent of operations"
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},
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{
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"MetricExpr": "L3D_CACHE_REFILL / INST_RETIRED * 1000",
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"BriefDescription": "The rate of L3 D-Cache misses per kilo instructions",
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"MetricGroup": "MPKI;L3_Cache_Effectiveness",
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"MetricName": "l3d_cache_mpki",
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"ScaleUnit": "1MPKI"
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},
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{
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"MetricExpr": "L3D_CACHE_REFILL / L3D_CACHE",
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"BriefDescription": "The rate of L3 D-Cache misses to the overall L3 D-Cache",
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"MetricGroup": "Miss_Ratio;L3_Cache_Effectiveness",
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"MetricName": "l3d_cache_miss_rate",
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"ScaleUnit": "100%"
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},
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{
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"MetricExpr": "BR_RETIRED / INST_RETIRED * 1000",
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"BriefDescription": "The rate of branches retired per kilo instructions",
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"MetricGroup": "MPKI;Branch_Effectiveness",
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"MetricName": "branch_pki",
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"ScaleUnit": "1PKI"
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},
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{
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"MetricExpr": "ipc / #slots",
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"BriefDescription": "IPC percentage of peak. The peak of IPC is the number of slots.",
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"MetricGroup": "General",
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"MetricName": "ipc_rate",
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"ScaleUnit": "100%"
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},
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{
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"MetricExpr": "INST_SPEC / CPU_CYCLES",
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"BriefDescription": "Speculatively executed Instructions Per Cycle (IPC)",
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"MetricGroup": "General",
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"MetricName": "spec_ipc"
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},
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{
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"MetricExpr": "OP_RETIRED / OP_SPEC",
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"BriefDescription": "Of all the micro-operations issued, what percentage are retired(committed)",
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"MetricGroup": "General",
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"MetricName": "retired_rate",
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"ScaleUnit": "100%"
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},
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{
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"MetricExpr": "1 - OP_RETIRED / OP_SPEC",
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"BriefDescription": "Of all the micro-operations issued, what percentage are not retired(committed)",
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"MetricGroup": "General",
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"MetricName": "wasted_rate",
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"ScaleUnit": "100%"
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},
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{
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"MetricExpr": "BR_IMMED_SPEC / INST_SPEC",
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"BriefDescription": "The rate of branch immediate instructions speculatively executed to overall instructions speculatively executed",
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"MetricGroup": "Operation_Mix",
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"MetricName": "branch_immed_spec_rate",
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"ScaleUnit": "100%"
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},
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{
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"MetricExpr": "BR_RETURN_SPEC / INST_SPEC",
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"BriefDescription": "The rate of procedure return instructions speculatively executed to overall instructions speculatively executed",
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"MetricGroup": "Operation_Mix",
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"MetricName": "branch_return_spec_rate",
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"ScaleUnit": "100%"
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},
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{
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"MetricExpr": "BR_INDIRECT_SPEC / INST_SPEC",
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"BriefDescription": "The rate of indirect branch instructions speculatively executed to overall instructions speculatively executed",
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"MetricGroup": "Operation_Mix",
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"MetricName": "branch_indirect_spec_rate",
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"ScaleUnit": "100%"
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},
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{
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"MetricName": "sve_all_percentage",
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"MetricExpr": "SVE_INST_SPEC / INST_SPEC * 100",
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"BriefDescription": "This metric measures scalable vector operations, including loads and stores, as a percentage of operations speculatively executed.",
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"MetricGroup": "Operation_Mix",
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"ScaleUnit": "1percent of operations"
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}
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]
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