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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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Add JSON files for AmpereOneX core PMU events and metrics. Reviewed-by: Ian Rogers <irogers@google.com> Signed-off-by: Ilkka Koskinen <ilkka@os.amperecomputing.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: John Garry <john.g.garry@oracle.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20231201021550.1109196-4-ilkka@os.amperecomputing.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
171 lines
6.9 KiB
JSON
171 lines
6.9 KiB
JSON
[
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{
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"PublicDescription": "Level 2 data translation buffer allocation",
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"EventCode": "0xD800",
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"EventName": "MMU_D_OTB_ALLOC",
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"BriefDescription": "Level 2 data translation buffer allocation"
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},
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{
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"PublicDescription": "Data TLB translation cache hit on S1L2 walk cache entry",
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"EventCode": "0xd801",
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"EventName": "MMU_D_TRANS_CACHE_HIT_S1L2_WALK",
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"BriefDescription": "Data TLB translation cache hit on S1L2 walk cache entry"
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},
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{
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"PublicDescription": "Data TLB translation cache hit on S1L1 walk cache entry",
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"EventCode": "0xd802",
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"EventName": "MMU_D_TRANS_CACHE_HIT_S1L1_WALK",
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"BriefDescription": "Data TLB translation cache hit on S1L1 walk cache entry"
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},
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{
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"PublicDescription": "Data TLB translation cache hit on S1L0 walk cache entry",
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"EventCode": "0xd803",
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"EventName": "MMU_D_TRANS_CACHE_HIT_S1L0_WALK",
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"BriefDescription": "Data TLB translation cache hit on S1L0 walk cache entry"
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},
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{
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"PublicDescription": "Data TLB translation cache hit on S2L2 walk cache entry",
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"EventCode": "0xd804",
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"EventName": "MMU_D_TRANS_CACHE_HIT_S2L2_WALK",
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"BriefDescription": "Data TLB translation cache hit on S2L2 walk cache entry"
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},
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{
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"PublicDescrition": "Data TLB translation cache hit on S2L1 walk cache entry",
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"EventCode": "0xd805",
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"EventName": "MMU_D_TRANS_CACHE_HIT_S2L1_WALK",
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"BriefDescription": "Data TLB translation cache hit on S2L1 walk cache entry"
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},
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{
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"PublicDescrition": "Data TLB translation cache hit on S2L0 walk cache entry",
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"EventCode": "0xd806",
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"EventName": "MMU_D_TRANS_CACHE_HIT_S2L0_WALK",
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"BriefDescription": "Data TLB translation cache hit on S2L0 walk cache entry"
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},
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{
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"PublicDescrition": "Data-side S1 page walk cache lookup",
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"EventCode": "0xd807",
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"EventName": "MMU_D_S1_WALK_CACHE_LOOKUP",
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"BriefDescription": "Data-side S1 page walk cache lookup"
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},
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{
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"PublicDescrition": "Data-side S1 page walk cache refill",
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"EventCode": "0xd808",
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"EventName": "MMU_D_S1_WALK_CACHE_REFILL",
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"BriefDescription": "Data-side S1 page walk cache refill"
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},
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{
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"PublicDescrition": "Data-side S2 page walk cache lookup",
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"EventCode": "0xd809",
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"EventName": "MMU_D_S2_WALK_CACHE_LOOKUP",
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"BriefDescription": "Data-side S2 page walk cache lookup"
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},
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{
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"PublicDescrition": "Data-side S2 page walk cache refill",
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"EventCode": "0xd80a",
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"EventName": "MMU_D_S2_WALK_CACHE_REFILL",
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"BriefDescription": "Data-side S2 page walk cache refill"
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},
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{
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"PublicDescription": "Data-side S1 table walk fault",
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"EventCode": "0xD80B",
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"EventName": "MMU_D_S1_WALK_FAULT",
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"BriefDescription": "Data-side S1 table walk fault"
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},
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{
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"PublicDescription": "Data-side S2 table walk fault",
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"EventCode": "0xD80C",
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"EventName": "MMU_D_S2_WALK_FAULT",
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"BriefDescription": "Data-side S2 table walk fault"
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},
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{
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"PublicDescription": "Data-side table walk steps or descriptor fetches",
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"EventCode": "0xD80D",
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"EventName": "MMU_D_WALK_STEPS",
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"BriefDescription": "Data-side table walk steps or descriptor fetches"
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},
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{
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"PublicDescription": "Level 2 instruction translation buffer allocation",
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"EventCode": "0xD900",
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"EventName": "MMU_I_OTB_ALLOC",
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"BriefDescription": "Level 2 instruction translation buffer allocation"
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},
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{
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"PublicDescrition": "Instruction TLB translation cache hit on S1L2 walk cache entry",
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"EventCode": "0xd901",
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"EventName": "MMU_I_TRANS_CACHE_HIT_S1L2_WALK",
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"BriefDescription": "Instruction TLB translation cache hit on S1L2 walk cache entry"
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},
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{
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"PublicDescrition": "Instruction TLB translation cache hit on S1L1 walk cache entry",
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"EventCode": "0xd902",
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"EventName": "MMU_I_TRANS_CACHE_HIT_S1L1_WALK",
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"BriefDescription": "Instruction TLB translation cache hit on S1L1 walk cache entry"
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},
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{
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"PublicDescrition": "Instruction TLB translation cache hit on S1L0 walk cache entry",
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"EventCode": "0xd903",
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"EventName": "MMU_I_TRANS_CACHE_HIT_S1L0_WALK",
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"BriefDescription": "Instruction TLB translation cache hit on S1L0 walk cache entry"
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},
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{
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"PublicDescrition": "Instruction TLB translation cache hit on S2L2 walk cache entry",
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"EventCode": "0xd904",
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"EventName": "MMU_I_TRANS_CACHE_HIT_S2L2_WALK",
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"BriefDescription": "Instruction TLB translation cache hit on S2L2 walk cache entry"
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},
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{
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"PublicDescrition": "Instruction TLB translation cache hit on S2L1 walk cache entry",
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"EventCode": "0xd905",
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"EventName": "MMU_I_TRANS_CACHE_HIT_S2L1_WALK",
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"BriefDescription": "Instruction TLB translation cache hit on S2L1 walk cache entry"
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},
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{
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"PublicDescrition": "Instruction TLB translation cache hit on S2L0 walk cache entry",
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"EventCode": "0xd906",
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"EventName": "MMU_I_TRANS_CACHE_HIT_S2L0_WALK",
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"BriefDescription": "Instruction TLB translation cache hit on S2L0 walk cache entry"
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},
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{
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"PublicDescrition": "Instruction-side S1 page walk cache lookup",
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"EventCode": "0xd907",
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"EventName": "MMU_I_S1_WALK_CACHE_LOOKUP",
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"BriefDescription": "Instruction-side S1 page walk cache lookup"
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},
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{
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"PublicDescrition": "Instruction-side S1 page walk cache refill",
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"EventCode": "0xd908",
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"EventName": "MMU_I_S1_WALK_CACHE_REFILL",
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"BriefDescription": "Instruction-side S1 page walk cache refill"
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},
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{
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"PublicDescrition": "Instruction-side S2 page walk cache lookup",
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"EventCode": "0xd909",
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"EventName": "MMU_I_S2_WALK_CACHE_LOOKUP",
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"BriefDescription": "Instruction-side S2 page walk cache lookup"
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},
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{
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"PublicDescrition": "Instruction-side S2 page walk cache refill",
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"EventCode": "0xd90a",
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"EventName": "MMU_I_S2_WALK_CACHE_REFILL",
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"BriefDescription": "Instruction-side S2 page walk cache refill"
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},
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{
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"PublicDescription": "Instruction-side S1 table walk fault",
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"EventCode": "0xD90B",
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"EventName": "MMU_I_S1_WALK_FAULT",
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"BriefDescription": "Instruction-side S1 table walk fault"
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},
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{
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"PublicDescription": "Instruction-side S2 table walk fault",
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"EventCode": "0xD90C",
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"EventName": "MMU_I_S2_WALK_FAULT",
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"BriefDescription": "Instruction-side S2 table walk fault"
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},
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{
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"PublicDescription": "Instruction-side table walk steps or descriptor fetches",
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"EventCode": "0xD90D",
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"EventName": "MMU_I_WALK_STEPS",
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"BriefDescription": "Instruction-side table walk steps or descriptor fetches"
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}
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]
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