mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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7d852b34be
Tegra264 supports max 32 channels, hence calculating the max bandwidth using the channel info from soc_data. Signed-off-by: Sheetal <sheetal@nvidia.com> Link: https://patch.msgid.link/20250512051747.1026770-12-sheetal@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
131 lines
3.7 KiB
C
131 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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// SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES.
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// All rights reserved.
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//
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// ADMA bandwidth calculation
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#include <linux/interconnect.h>
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#include <linux/module.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include "tegra_isomgr_bw.h"
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#include "tegra210_admaif.h"
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#define MAX_SAMPLE_RATE 192 /* KHz*/
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#define MAX_BYTES_PER_SAMPLE 4
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int tegra_isomgr_adma_setbw(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai, bool is_running)
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{
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struct device *dev = dai->dev;
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struct tegra_admaif *admaif = snd_soc_dai_get_drvdata(dai);
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struct tegra_adma_isomgr *adma_isomgr = admaif->adma_isomgr;
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struct snd_pcm_runtime *runtime = substream->runtime;
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struct snd_pcm *pcm = substream->pcm;
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u32 type = substream->stream, bandwidth = 0;
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int sample_bytes;
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if (!adma_isomgr)
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return 0;
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if (!runtime || !pcm)
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return -EINVAL;
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if (pcm->device >= adma_isomgr->max_pcm_device) {
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dev_err(dev, "%s: PCM device number %d is greater than %d\n", __func__,
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pcm->device, adma_isomgr->max_pcm_device);
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return -EINVAL;
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}
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/*
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* No action if stream is running and bandwidth is already set or
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* stream is not running and bandwidth is already reset
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*/
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if ((adma_isomgr->bw_per_dev[type][pcm->device] && is_running) ||
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(!adma_isomgr->bw_per_dev[type][pcm->device] && !is_running))
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return 0;
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if (is_running) {
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sample_bytes = snd_pcm_format_width(runtime->format) / 8;
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if (sample_bytes < 0)
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return sample_bytes;
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/* KB/s kilo bytes per sec */
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bandwidth = runtime->channels * (runtime->rate / 1000) *
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sample_bytes;
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}
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mutex_lock(&adma_isomgr->mutex);
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if (is_running) {
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if (bandwidth + adma_isomgr->current_bandwidth > adma_isomgr->max_bw)
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bandwidth = adma_isomgr->max_bw - adma_isomgr->current_bandwidth;
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adma_isomgr->current_bandwidth += bandwidth;
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} else {
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adma_isomgr->current_bandwidth -= adma_isomgr->bw_per_dev[type][pcm->device];
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}
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mutex_unlock(&adma_isomgr->mutex);
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adma_isomgr->bw_per_dev[type][pcm->device] = bandwidth;
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dev_dbg(dev, "Setting up bandwidth to %d KBps\n", adma_isomgr->current_bandwidth);
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return icc_set_bw(adma_isomgr->icc_path_handle,
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adma_isomgr->current_bandwidth, adma_isomgr->max_bw);
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}
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int tegra_isomgr_adma_register(struct device *dev)
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{
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struct tegra_admaif *admaif = dev_get_drvdata(dev);
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struct tegra_adma_isomgr *adma_isomgr;
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int i;
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adma_isomgr = devm_kzalloc(dev, sizeof(struct tegra_adma_isomgr), GFP_KERNEL);
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if (!adma_isomgr)
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return -ENOMEM;
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adma_isomgr->icc_path_handle = devm_of_icc_get(dev, "write");
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if (IS_ERR(adma_isomgr->icc_path_handle))
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return dev_err_probe(dev, PTR_ERR(adma_isomgr->icc_path_handle),
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"failed to acquire interconnect path\n");
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/* Either INTERCONNECT config OR interconnect property is not defined */
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if (!adma_isomgr->icc_path_handle) {
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devm_kfree(dev, adma_isomgr);
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return 0;
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}
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adma_isomgr->max_pcm_device = admaif->soc_data->num_ch;
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adma_isomgr->max_bw = STREAM_TYPE * MAX_SAMPLE_RATE * MAX_BYTES_PER_SAMPLE *
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admaif->soc_data->max_stream_ch * adma_isomgr->max_pcm_device;
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for (i = 0; i < STREAM_TYPE; i++) {
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adma_isomgr->bw_per_dev[i] = devm_kzalloc(dev, adma_isomgr->max_pcm_device *
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sizeof(u32), GFP_KERNEL);
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if (!adma_isomgr->bw_per_dev[i])
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return -ENOMEM;
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}
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adma_isomgr->current_bandwidth = 0;
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mutex_init(&adma_isomgr->mutex);
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admaif->adma_isomgr = adma_isomgr;
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return 0;
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}
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void tegra_isomgr_adma_unregister(struct device *dev)
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{
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struct tegra_admaif *admaif = dev_get_drvdata(dev);
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if (!admaif->adma_isomgr)
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return;
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mutex_destroy(&admaif->adma_isomgr->mutex);
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}
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MODULE_AUTHOR("Mohan Kumar <mkumard@nvidia.com>");
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MODULE_DESCRIPTION("Tegra ADMA Bandwidth Request driver");
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MODULE_LICENSE("GPL");
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