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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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4152d33ab1
Add Tegra264 AHUB support with following changes: - Update Tegra264 IP instances: DMIC(2), DSPK(1), AMX(6), ADX(6), I2S(8). - Update register offsets for Tegra264. - Add soc_data for Tegra264 chip-specific variations. - Increase channels_max to 32 for Tegra264 DAIs. Signed-off-by: Sheetal <sheetal@nvidia.com> Link: https://patch.msgid.link/20250512051747.1026770-11-sheetal@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
172 lines
5.7 KiB
C
172 lines
5.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* tegra210_ahub.h - TEGRA210 AHUB
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*
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* Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved.
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*
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*/
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#ifndef __TEGRA210_AHUB__H__
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#define __TEGRA210_AHUB__H__
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/* Tegra210 specific */
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#define TEGRA210_XBAR_PART1_RX 0x200
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#define TEGRA210_XBAR_PART2_RX 0x400
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#define TEGRA210_XBAR_RX_STRIDE 0x4
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#define TEGRA210_XBAR_AUDIO_RX_COUNT 90
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#define TEGRA210_XBAR_REG_MASK_0 0xf1f03ff
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#define TEGRA210_XBAR_REG_MASK_1 0x3f30031f
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#define TEGRA210_XBAR_REG_MASK_2 0xff1cf313
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#define TEGRA210_XBAR_REG_MASK_3 0x0
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#define TEGRA210_XBAR_UPDATE_MAX_REG 3
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/* Tegra186 specific */
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#define TEGRA186_XBAR_PART3_RX 0x600
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#define TEGRA186_XBAR_AUDIO_RX_COUNT 115
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#define TEGRA186_XBAR_REG_MASK_0 0xf3fffff
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#define TEGRA186_XBAR_REG_MASK_1 0x3f310f1f
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#define TEGRA186_XBAR_REG_MASK_2 0xff3cf311
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#define TEGRA186_XBAR_REG_MASK_3 0x3f0f00ff
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#define TEGRA186_XBAR_UPDATE_MAX_REG 4
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/* Tegra264 specific */
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#define TEGRA264_XBAR_PART1_RX 0x1000
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#define TEGRA264_XBAR_PART2_RX 0x2000
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#define TEGRA264_XBAR_PART3_RX 0x3000
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#define TEGRA264_XBAR_PART4_RX 0x4000
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#define TEGRA264_XBAR_PART0_ADX6_RX1 0x224
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#define TEGRA264_XBAR_AUDIO_RX_COUNT ((TEGRA264_XBAR_PART0_ADX6_RX1 / 4) + 1)
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#define TEGRA264_XBAR_REG_MASK_0 0xfffffff
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#define TEGRA264_XBAR_REG_MASK_1 0x3f013f1f
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#define TEGRA264_XBAR_REG_MASK_2 0xff3c0301
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#define TEGRA264_XBAR_REG_MASK_3 0x3f00ffff
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#define TEGRA264_XBAR_REG_MASK_4 0x7fff9f
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#define TEGRA264_XBAR_UPDATE_MAX_REG 5
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#define TEGRA264_AXBAR_ADMAIF_RX1 0x0
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#define TEGRA264_AXBAR_SFC4_RX1 0x6c
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#define TEGRA264_AXBAR_MIXER1_RX1 0x80
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#define TEGRA264_AXBAR_MIXER1_RX10 0xa4
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#define TEGRA264_AXBAR_DSPK1_RX1 0xc0
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#define TEGRA264_AXBAR_OPE1_RX1 0x100
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#define TEGRA264_AXBAR_MVC1_RX1 0x110
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#define TEGRA264_AXBAR_MVC2_RX1 0x114
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#define TEGRA264_AXBAR_AMX1_RX1 0x120
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#define TEGRA264_AXBAR_AMX3_RX4 0x14c
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#define TEGRA264_AXBAR_ADX1_RX1 0x160
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#define TEGRA264_AXBAR_ASRC1_RX7 0x1a8
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#define TEGRA264_AXBAR_ADMAIF_RX21 0x1d0
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#define TEGRA264_AXBAR_ADX6_RX1 0x224
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#define TEGRA_XBAR_UPDATE_MAX_REG (TEGRA264_XBAR_UPDATE_MAX_REG)
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#define TEGRA264_MAX_REGISTER_ADDR (TEGRA264_XBAR_PART4_RX + \
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(TEGRA210_XBAR_RX_STRIDE * (TEGRA264_XBAR_AUDIO_RX_COUNT - 1)))
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#define TEGRA186_MAX_REGISTER_ADDR (TEGRA186_XBAR_PART3_RX + \
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(TEGRA210_XBAR_RX_STRIDE * (TEGRA186_XBAR_AUDIO_RX_COUNT - 1)))
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#define TEGRA210_MAX_REGISTER_ADDR (TEGRA210_XBAR_PART2_RX + \
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(TEGRA210_XBAR_RX_STRIDE * (TEGRA210_XBAR_AUDIO_RX_COUNT - 1)))
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#define MUX_REG(id) (TEGRA210_XBAR_RX_STRIDE * (id))
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#define MUX_VALUE(npart, nbit) (1 + (nbit) + (npart) * 32)
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#define SOC_VALUE_ENUM_WIDE(xreg, shift, xmax, xtexts, xvalues) \
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{ \
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.reg = xreg, \
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.shift_l = shift, \
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.shift_r = shift, \
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.items = xmax, \
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.texts = xtexts, \
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.values = xvalues, \
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.mask = xmax ? roundup_pow_of_two(xmax) - 1 : 0 \
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}
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#define SOC_VALUE_ENUM_WIDE_DECL(name, xreg, shift, xtexts, xvalues) \
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static struct soc_enum name = \
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SOC_VALUE_ENUM_WIDE(xreg, shift, ARRAY_SIZE(xtexts), \
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xtexts, xvalues)
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#define MUX_ENUM_CTRL_DECL(ename, id) \
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SOC_VALUE_ENUM_WIDE_DECL(ename##_enum, MUX_REG(id), 0, \
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tegra210_ahub_mux_texts, \
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tegra210_ahub_mux_values); \
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static const struct snd_kcontrol_new ename##_control = \
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SOC_DAPM_ENUM_EXT("Route", ename##_enum, \
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tegra_ahub_get_value_enum, \
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tegra_ahub_put_value_enum)
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#define MUX_ENUM_CTRL_DECL_186(ename, id) \
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SOC_VALUE_ENUM_WIDE_DECL(ename##_enum, MUX_REG(id), 0, \
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tegra186_ahub_mux_texts, \
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tegra186_ahub_mux_values); \
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static const struct snd_kcontrol_new ename##_control = \
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SOC_DAPM_ENUM_EXT("Route", ename##_enum, \
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tegra_ahub_get_value_enum, \
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tegra_ahub_put_value_enum)
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#define MUX_ENUM_CTRL_DECL_234(ename, id) MUX_ENUM_CTRL_DECL_186(ename, id)
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#define MUX_ENUM_CTRL_DECL_264(ename, id) \
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SOC_VALUE_ENUM_WIDE_DECL(ename##_enum, MUX_REG(id), 0, \
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tegra264_ahub_mux_texts, \
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tegra264_ahub_mux_values); \
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static const struct snd_kcontrol_new ename##_control = \
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SOC_DAPM_ENUM_EXT("Route", ename##_enum, \
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tegra_ahub_get_value_enum, \
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tegra_ahub_put_value_enum)
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#define WIDGETS(sname, ename) \
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SND_SOC_DAPM_AIF_IN(sname " XBAR-RX", NULL, 0, SND_SOC_NOPM, 0, 0), \
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SND_SOC_DAPM_AIF_OUT(sname " XBAR-TX", NULL, 0, SND_SOC_NOPM, 0, 0), \
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SND_SOC_DAPM_MUX(sname " Mux", SND_SOC_NOPM, 0, 0, \
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&ename##_control)
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#define TX_WIDGETS(sname) \
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SND_SOC_DAPM_AIF_IN(sname " XBAR-RX", NULL, 0, SND_SOC_NOPM, 0, 0), \
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SND_SOC_DAPM_AIF_OUT(sname " XBAR-TX", NULL, 0, SND_SOC_NOPM, 0, 0)
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#define DAI(sname) \
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{ \
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.name = "XBAR-" #sname, \
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.playback = { \
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.stream_name = #sname " XBAR-Playback", \
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.channels_min = 1, \
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.channels_max = 32, \
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.rates = SNDRV_PCM_RATE_8000_192000, \
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.formats = SNDRV_PCM_FMTBIT_S8 | \
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SNDRV_PCM_FMTBIT_S16_LE | \
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SNDRV_PCM_FMTBIT_S24_LE | \
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SNDRV_PCM_FMTBIT_S32_LE, \
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}, \
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.capture = { \
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.stream_name = #sname " XBAR-Capture", \
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.channels_min = 1, \
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.channels_max = 32, \
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.rates = SNDRV_PCM_RATE_8000_192000, \
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.formats = SNDRV_PCM_FMTBIT_S8 | \
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SNDRV_PCM_FMTBIT_S16_LE | \
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SNDRV_PCM_FMTBIT_S24_LE | \
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SNDRV_PCM_FMTBIT_S32_LE, \
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}, \
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}
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struct tegra_ahub_soc_data {
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const struct regmap_config *regmap_config;
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const struct snd_soc_component_driver *cmpnt_drv;
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struct snd_soc_dai_driver *dai_drv;
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unsigned int mask[TEGRA_XBAR_UPDATE_MAX_REG];
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unsigned int reg_count;
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unsigned int num_dais;
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unsigned int xbar_part_size;
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};
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struct tegra_ahub {
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const struct tegra_ahub_soc_data *soc_data;
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struct regmap *regmap;
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struct clk *clk;
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};
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#endif
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