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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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af1c968d25
Define handlers specific to ACE platforms, that Frisco Lake (FCL), a PantherLake (PTL)-based platform, is founded upon. Most operations are still inherited from their predecessors with the major difference being AudioDSP cores management - replaced by DSP-domain power management. Software has to ensure the DSP domain is both powered on and its power-gating disabled before it can be utilized for streaming. Reviewed-by: Amadeusz Sławiński <amadeuszx.slawinski@linux.intel.com> Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com> Acked-by: Liam Girdwood <liam.r.girdwood@linux.intel.com> Link: https://patch.msgid.link/20250407112352.3720779-6-cezary.rojewski@intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
99 lines
3.0 KiB
C
99 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright(c) 2024-2025 Intel Corporation
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*
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* Authors: Cezary Rojewski <cezary.rojewski@intel.com>
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* Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
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*/
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#include <sound/hdaudio_ext.h>
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#include "avs.h"
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#include "registers.h"
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#include "trace.h"
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#define MTL_HfDSSGBL_BASE 0x1000
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#define MTL_REG_HfDSSCS (MTL_HfDSSGBL_BASE + 0x0)
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#define MTL_HfDSSCS_SPA BIT(16)
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#define MTL_HfDSSCS_CPA BIT(24)
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#define MTL_DSPCS_BASE 0x178D00
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#define MTL_REG_DSPCCTL (MTL_DSPCS_BASE + 0x4)
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#define MTL_DSPCCTL_OSEL GENMASK(25, 24)
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#define MTL_DSPCCTL_OSEL_HOST BIT(25)
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static int avs_ptl_core_power_on(struct avs_dev *adev)
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{
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u32 reg;
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int ret;
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/* Power up DSP domain. */
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snd_hdac_adsp_updatel(adev, MTL_REG_HfDSSCS, MTL_HfDSSCS_SPA, MTL_HfDSSCS_SPA);
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trace_avs_dsp_core_op(1, AVS_MAIN_CORE_MASK, "power dsp", true);
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ret = snd_hdac_adsp_readl_poll(adev, MTL_REG_HfDSSCS, reg,
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(reg & MTL_HfDSSCS_CPA) == MTL_HfDSSCS_CPA,
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AVS_ADSPCS_INTERVAL_US, AVS_ADSPCS_TIMEOUT_US);
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if (ret) {
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dev_err(adev->dev, "power on domain dsp failed: %d\n", ret);
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return ret;
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}
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/* Prevent power gating of DSP domain. */
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snd_hdac_adsp_updatel(adev, MTL_REG_HfPWRCTL2, MTL_HfPWRCTL2_WPDSPHPxPG,
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MTL_HfPWRCTL2_WPDSPHPxPG);
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trace_avs_dsp_core_op(1, AVS_MAIN_CORE_MASK, "prevent dsp PG", true);
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ret = snd_hdac_adsp_readl_poll(adev, MTL_REG_HfPWRSTS2, reg,
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(reg & MTL_HfPWRSTS2_DSPHPxPGS) == MTL_HfPWRSTS2_DSPHPxPGS,
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AVS_ADSPCS_INTERVAL_US, AVS_ADSPCS_TIMEOUT_US);
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/* Set ownership to HOST. */
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snd_hdac_adsp_updatel(adev, MTL_REG_DSPCCTL, MTL_DSPCCTL_OSEL, MTL_DSPCCTL_OSEL_HOST);
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return ret;
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}
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static int avs_ptl_core_power_off(struct avs_dev *adev)
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{
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u32 reg;
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/* Allow power gating of DSP domain. No STS polling as HOST is only one of its users. */
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snd_hdac_adsp_updatel(adev, MTL_REG_HfPWRCTL2, MTL_HfPWRCTL2_WPDSPHPxPG, 0);
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trace_avs_dsp_core_op(0, AVS_MAIN_CORE_MASK, "allow dsp pg", false);
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/* Power down DSP domain. */
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snd_hdac_adsp_updatel(adev, MTL_REG_HfDSSCS, MTL_HfDSSCS_SPA, 0);
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trace_avs_dsp_core_op(0, AVS_MAIN_CORE_MASK, "power dsp", false);
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return snd_hdac_adsp_readl_poll(adev, MTL_REG_HfDSSCS, reg,
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(reg & MTL_HfDSSCS_CPA) == 0,
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AVS_ADSPCS_INTERVAL_US, AVS_ADSPCS_TIMEOUT_US);
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}
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static int avs_ptl_core_power(struct avs_dev *adev, u32 core_mask, bool power)
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{
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core_mask &= AVS_MAIN_CORE_MASK;
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if (!core_mask)
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return 0;
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if (power)
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return avs_ptl_core_power_on(adev);
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return avs_ptl_core_power_off(adev);
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}
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const struct avs_dsp_ops avs_ptl_dsp_ops = {
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.power = avs_ptl_core_power,
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.reset = avs_mtl_core_reset,
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.stall = avs_lnl_core_stall,
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.dsp_interrupt = avs_mtl_dsp_interrupt,
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.int_control = avs_mtl_interrupt_control,
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.load_basefw = avs_hda_load_basefw,
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.load_lib = avs_hda_load_library,
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.transfer_mods = avs_hda_transfer_modules,
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.log_buffer_offset = avs_icl_log_buffer_offset,
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.log_buffer_status = avs_apl_log_buffer_status,
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.coredump = avs_apl_coredump,
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.d0ix_toggle = avs_icl_d0ix_toggle,
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.set_d0ix = avs_icl_set_d0ix,
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AVS_SET_ENABLE_LOGS_OP(icl)
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};
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