mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-01 23:46:45 +00:00

Perf and PMU updates: - Add support for new (v3) Hisilicon SLLC and DDRC PMUs - Add support for Arm-NI PMU integrations that share interrupts between clock domains within a given instance - Allow SPE to be configured with a lower sample period than the minimum recommendation advertised by PMSIDR_EL1.Interval - Add suppport for Arm's "Branch Record Buffer Extension" (BRBE) - Adjust the perf watchdog period according to cpu frequency changes - Minor driver fixes and cleanups Hardware features: - Support for MTE store-only checking (FEAT_MTE_STORE_ONLY) - Support for reporting the non-address bits during a synchronous MTE tag check fault (FEAT_MTE_TAGGED_FAR) - Optimise the TLBI when folding/unfolding contiguous PTEs on hardware with FEAT_BBM (break-before-make) level 2 and no TLB conflict aborts Software features: - Enable HAVE_LIVEPATCH after implementing arch_stack_walk_reliable() and using the text-poke API for late module relocations - Force VMAP_STACK always on and change arm64_efi_rt_init() to use arch_alloc_vmap_stack() in order to avoid KASAN false positives ACPI: - Improve SPCR handling and messaging on systems lacking an SPCR table Debug: - Simplify the debug exception entry path - Drop redundant DBG_MDSCR_* macros Kselftests: - Cleanups and improvements for SME, SVE and FPSIMD tests Miscellaneous: - Optimise loop to reduce redundant operations in contpte_ptep_get() - Remove ISB when resetting POR_EL0 during signal handling - Mark the kernel as tainted on SEA and SError panic - Remove redundant gcs_free() call -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE5RElWfyWxS+3PLO2a9axLQDIXvEFAmiDkgoACgkQa9axLQDI XvFucQ//bYugRP5/Sdlrq5eDKWBGi1HufYzwfDEBLc4S75Eu8mGL/tuThfu9yFn+ qCowtt4U84HdWsZDTSVo6lym6v2vJUpGOMgXzepvJaFBRnqGv9X9NxH6RQO1LTnu Pm7rO+7I9tNpfuc7Zu9pHDggsJEw+WzVfmEF6WPSFlT9mUNv6NbSx4rbLQKU86Dm ouTqXaePEQZ5oiRXVasxyT0otGtiACD20WpgOtNjYGzsfUVwCf/C83V/2DLwwbhr 9cW9lCtFxA/yFdQcA9ThRzWZ9Eo5LAHqjGIq00+zOjuzgDbBtcTT79gpChkhovIR FBIsWHd9j9i3nYxzf4V4eRKQnyqS3NQWv7g7uKFwNgARif1Zk0VJ77QIlAYk5xLI ENTRjLKz5WNGGnhdkeCvDlVyxX+OktgcVTp3vqRxAKCRahMMUqBrwxiM8RzVF37e yzkEQayL8F7uZqy9H7Sjn48UpHZux6frJ1bBQw1oEvR9QmAoAdqavPMSAYIOT3Zr ze4WIljq/cFr3kBPIFP5pK1e0qYMHXZpSKIm8MAv6y/7KmQuVbMjZthpuPbLSIw0 Q7C0KalB8lToPIbO7qMni/he0dCN4K2+E1YHFTR+pzfcoLuW4rjSg7i8tqMLKMJ8 H+SeGLyPtM5A6bdAPTTpqefcgUUe7064ENUqrGUpDEynGXA7boE= =5h1C -----END PGP SIGNATURE----- Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 updates from Catalin Marinas: "A quick summary: perf support for Branch Record Buffer Extensions (BRBE), typical PMU hardware updates, small additions to MTE for store-only tag checking and exposing non-address bits to signal handlers, HAVE_LIVEPATCH enabled on arm64, VMAP_STACK forced on. There is also a TLBI optimisation on hardware that does not require break-before-make when changing the user PTEs between contiguous and non-contiguous. More details: Perf and PMU updates: - Add support for new (v3) Hisilicon SLLC and DDRC PMUs - Add support for Arm-NI PMU integrations that share interrupts between clock domains within a given instance - Allow SPE to be configured with a lower sample period than the minimum recommendation advertised by PMSIDR_EL1.Interval - Add suppport for Arm's "Branch Record Buffer Extension" (BRBE) - Adjust the perf watchdog period according to cpu frequency changes - Minor driver fixes and cleanups Hardware features: - Support for MTE store-only checking (FEAT_MTE_STORE_ONLY) - Support for reporting the non-address bits during a synchronous MTE tag check fault (FEAT_MTE_TAGGED_FAR) - Optimise the TLBI when folding/unfolding contiguous PTEs on hardware with FEAT_BBM (break-before-make) level 2 and no TLB conflict aborts Software features: - Enable HAVE_LIVEPATCH after implementing arch_stack_walk_reliable() and using the text-poke API for late module relocations - Force VMAP_STACK always on and change arm64_efi_rt_init() to use arch_alloc_vmap_stack() in order to avoid KASAN false positives ACPI: - Improve SPCR handling and messaging on systems lacking an SPCR table Debug: - Simplify the debug exception entry path - Drop redundant DBG_MDSCR_* macros Kselftests: - Cleanups and improvements for SME, SVE and FPSIMD tests Miscellaneous: - Optimise loop to reduce redundant operations in contpte_ptep_get() - Remove ISB when resetting POR_EL0 during signal handling - Mark the kernel as tainted on SEA and SError panic - Remove redundant gcs_free() call" * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (93 commits) arm64/gcs: task_gcs_el0_enable() should use passed task arm64: Kconfig: Keep selects somewhat alphabetically ordered arm64: signal: Remove ISB when resetting POR_EL0 kselftest/arm64: Handle attempts to disable SM on SME only systems kselftest/arm64: Fix SVE write data generation for SME only systems kselftest/arm64: Test SME on SME only systems in fp-ptrace kselftest/arm64: Test FPSIMD format data writes via NT_ARM_SVE in fp-ptrace kselftest/arm64: Allow sve-ptrace to run on SME only systems arm64/mm: Drop redundant addr increment in set_huge_pte_at() kselftest/arm4: Provide local defines for AT_HWCAP3 arm64: Mark kernel as tainted on SAE and SError panic arm64/gcs: Don't call gcs_free() when releasing task_struct drivers/perf: hisi: Support PMUs with no interrupt drivers/perf: hisi: Relax the event number check of v2 PMUs drivers/perf: hisi: Add support for HiSilicon SLLC v3 PMU driver drivers/perf: hisi: Use ACPI driver_data to retrieve SLLC PMU information drivers/perf: hisi: Add support for HiSilicon DDRC v3 PMU driver drivers/perf: hisi: Simplify the probe process for each DDRC version perf/arm-ni: Support sharing IRQs within an NI instance perf/arm-ni: Consolidate CPU affinity handling ...
380 lines
13 KiB
C
380 lines
13 KiB
C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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#ifndef _LINUX_PRCTL_H
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#define _LINUX_PRCTL_H
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#include <linux/types.h>
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/* Values to pass as first argument to prctl() */
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#define PR_SET_PDEATHSIG 1 /* Second arg is a signal */
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#define PR_GET_PDEATHSIG 2 /* Second arg is a ptr to return the signal */
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/* Get/set current->mm->dumpable */
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#define PR_GET_DUMPABLE 3
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#define PR_SET_DUMPABLE 4
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/* Get/set unaligned access control bits (if meaningful) */
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#define PR_GET_UNALIGN 5
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#define PR_SET_UNALIGN 6
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# define PR_UNALIGN_NOPRINT 1 /* silently fix up unaligned user accesses */
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# define PR_UNALIGN_SIGBUS 2 /* generate SIGBUS on unaligned user access */
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/* Get/set whether or not to drop capabilities on setuid() away from
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* uid 0 (as per security/commoncap.c) */
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#define PR_GET_KEEPCAPS 7
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#define PR_SET_KEEPCAPS 8
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/* Get/set floating-point emulation control bits (if meaningful) */
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#define PR_GET_FPEMU 9
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#define PR_SET_FPEMU 10
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# define PR_FPEMU_NOPRINT 1 /* silently emulate fp operations accesses */
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# define PR_FPEMU_SIGFPE 2 /* don't emulate fp operations, send SIGFPE instead */
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/* Get/set floating-point exception mode (if meaningful) */
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#define PR_GET_FPEXC 11
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#define PR_SET_FPEXC 12
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# define PR_FP_EXC_SW_ENABLE 0x80 /* Use FPEXC for FP exception enables */
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# define PR_FP_EXC_DIV 0x010000 /* floating point divide by zero */
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# define PR_FP_EXC_OVF 0x020000 /* floating point overflow */
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# define PR_FP_EXC_UND 0x040000 /* floating point underflow */
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# define PR_FP_EXC_RES 0x080000 /* floating point inexact result */
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# define PR_FP_EXC_INV 0x100000 /* floating point invalid operation */
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# define PR_FP_EXC_DISABLED 0 /* FP exceptions disabled */
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# define PR_FP_EXC_NONRECOV 1 /* async non-recoverable exc. mode */
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# define PR_FP_EXC_ASYNC 2 /* async recoverable exception mode */
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# define PR_FP_EXC_PRECISE 3 /* precise exception mode */
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/* Get/set whether we use statistical process timing or accurate timestamp
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* based process timing */
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#define PR_GET_TIMING 13
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#define PR_SET_TIMING 14
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# define PR_TIMING_STATISTICAL 0 /* Normal, traditional,
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statistical process timing */
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# define PR_TIMING_TIMESTAMP 1 /* Accurate timestamp based
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process timing */
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#define PR_SET_NAME 15 /* Set process name */
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#define PR_GET_NAME 16 /* Get process name */
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/* Get/set process endian */
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#define PR_GET_ENDIAN 19
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#define PR_SET_ENDIAN 20
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# define PR_ENDIAN_BIG 0
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# define PR_ENDIAN_LITTLE 1 /* True little endian mode */
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# define PR_ENDIAN_PPC_LITTLE 2 /* "PowerPC" pseudo little endian */
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/* Get/set process seccomp mode */
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#define PR_GET_SECCOMP 21
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#define PR_SET_SECCOMP 22
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/* Get/set the capability bounding set (as per security/commoncap.c) */
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#define PR_CAPBSET_READ 23
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#define PR_CAPBSET_DROP 24
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/* Get/set the process' ability to use the timestamp counter instruction */
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#define PR_GET_TSC 25
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#define PR_SET_TSC 26
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# define PR_TSC_ENABLE 1 /* allow the use of the timestamp counter */
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# define PR_TSC_SIGSEGV 2 /* throw a SIGSEGV instead of reading the TSC */
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/* Get/set securebits (as per security/commoncap.c) */
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#define PR_GET_SECUREBITS 27
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#define PR_SET_SECUREBITS 28
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/*
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* Get/set the timerslack as used by poll/select/nanosleep
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* A value of 0 means "use default"
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*/
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#define PR_SET_TIMERSLACK 29
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#define PR_GET_TIMERSLACK 30
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#define PR_TASK_PERF_EVENTS_DISABLE 31
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#define PR_TASK_PERF_EVENTS_ENABLE 32
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/*
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* Set early/late kill mode for hwpoison memory corruption.
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* This influences when the process gets killed on a memory corruption.
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*/
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#define PR_MCE_KILL 33
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# define PR_MCE_KILL_CLEAR 0
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# define PR_MCE_KILL_SET 1
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# define PR_MCE_KILL_LATE 0
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# define PR_MCE_KILL_EARLY 1
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# define PR_MCE_KILL_DEFAULT 2
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#define PR_MCE_KILL_GET 34
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/*
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* Tune up process memory map specifics.
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*/
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#define PR_SET_MM 35
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# define PR_SET_MM_START_CODE 1
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# define PR_SET_MM_END_CODE 2
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# define PR_SET_MM_START_DATA 3
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# define PR_SET_MM_END_DATA 4
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# define PR_SET_MM_START_STACK 5
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# define PR_SET_MM_START_BRK 6
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# define PR_SET_MM_BRK 7
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# define PR_SET_MM_ARG_START 8
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# define PR_SET_MM_ARG_END 9
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# define PR_SET_MM_ENV_START 10
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# define PR_SET_MM_ENV_END 11
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# define PR_SET_MM_AUXV 12
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# define PR_SET_MM_EXE_FILE 13
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# define PR_SET_MM_MAP 14
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# define PR_SET_MM_MAP_SIZE 15
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/*
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* This structure provides new memory descriptor
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* map which mostly modifies /proc/pid/stat[m]
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* output for a task. This mostly done in a
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* sake of checkpoint/restore functionality.
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*/
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struct prctl_mm_map {
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__u64 start_code; /* code section bounds */
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__u64 end_code;
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__u64 start_data; /* data section bounds */
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__u64 end_data;
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__u64 start_brk; /* heap for brk() syscall */
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__u64 brk;
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__u64 start_stack; /* stack starts at */
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__u64 arg_start; /* command line arguments bounds */
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__u64 arg_end;
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__u64 env_start; /* environment variables bounds */
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__u64 env_end;
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__u64 *auxv; /* auxiliary vector */
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__u32 auxv_size; /* vector size */
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__u32 exe_fd; /* /proc/$pid/exe link file */
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};
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/*
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* Set specific pid that is allowed to ptrace the current task.
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* A value of 0 mean "no process".
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*/
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#define PR_SET_PTRACER 0x59616d61
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# define PR_SET_PTRACER_ANY ((unsigned long)-1)
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#define PR_SET_CHILD_SUBREAPER 36
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#define PR_GET_CHILD_SUBREAPER 37
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/*
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* If no_new_privs is set, then operations that grant new privileges (i.e.
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* execve) will either fail or not grant them. This affects suid/sgid,
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* file capabilities, and LSMs.
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*
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* Operations that merely manipulate or drop existing privileges (setresuid,
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* capset, etc.) will still work. Drop those privileges if you want them gone.
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*
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* Changing LSM security domain is considered a new privilege. So, for example,
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* asking selinux for a specific new context (e.g. with runcon) will result
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* in execve returning -EPERM.
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*
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* See Documentation/userspace-api/no_new_privs.rst for more details.
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*/
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#define PR_SET_NO_NEW_PRIVS 38
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#define PR_GET_NO_NEW_PRIVS 39
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#define PR_GET_TID_ADDRESS 40
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#define PR_SET_THP_DISABLE 41
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#define PR_GET_THP_DISABLE 42
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/*
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* No longer implemented, but left here to ensure the numbers stay reserved:
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*/
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#define PR_MPX_ENABLE_MANAGEMENT 43
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#define PR_MPX_DISABLE_MANAGEMENT 44
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#define PR_SET_FP_MODE 45
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#define PR_GET_FP_MODE 46
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# define PR_FP_MODE_FR (1 << 0) /* 64b FP registers */
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# define PR_FP_MODE_FRE (1 << 1) /* 32b compatibility */
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/* Control the ambient capability set */
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#define PR_CAP_AMBIENT 47
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# define PR_CAP_AMBIENT_IS_SET 1
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# define PR_CAP_AMBIENT_RAISE 2
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# define PR_CAP_AMBIENT_LOWER 3
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# define PR_CAP_AMBIENT_CLEAR_ALL 4
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/* arm64 Scalable Vector Extension controls */
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/* Flag values must be kept in sync with ptrace NT_ARM_SVE interface */
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#define PR_SVE_SET_VL 50 /* set task vector length */
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# define PR_SVE_SET_VL_ONEXEC (1 << 18) /* defer effect until exec */
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#define PR_SVE_GET_VL 51 /* get task vector length */
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/* Bits common to PR_SVE_SET_VL and PR_SVE_GET_VL */
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# define PR_SVE_VL_LEN_MASK 0xffff
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# define PR_SVE_VL_INHERIT (1 << 17) /* inherit across exec */
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/* Per task speculation control */
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#define PR_GET_SPECULATION_CTRL 52
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#define PR_SET_SPECULATION_CTRL 53
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/* Speculation control variants */
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# define PR_SPEC_STORE_BYPASS 0
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# define PR_SPEC_INDIRECT_BRANCH 1
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# define PR_SPEC_L1D_FLUSH 2
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/* Return and control values for PR_SET/GET_SPECULATION_CTRL */
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# define PR_SPEC_NOT_AFFECTED 0
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# define PR_SPEC_PRCTL (1UL << 0)
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# define PR_SPEC_ENABLE (1UL << 1)
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# define PR_SPEC_DISABLE (1UL << 2)
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# define PR_SPEC_FORCE_DISABLE (1UL << 3)
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# define PR_SPEC_DISABLE_NOEXEC (1UL << 4)
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/* Reset arm64 pointer authentication keys */
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#define PR_PAC_RESET_KEYS 54
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# define PR_PAC_APIAKEY (1UL << 0)
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# define PR_PAC_APIBKEY (1UL << 1)
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# define PR_PAC_APDAKEY (1UL << 2)
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# define PR_PAC_APDBKEY (1UL << 3)
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# define PR_PAC_APGAKEY (1UL << 4)
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/* Tagged user address controls for arm64 and RISC-V */
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#define PR_SET_TAGGED_ADDR_CTRL 55
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#define PR_GET_TAGGED_ADDR_CTRL 56
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# define PR_TAGGED_ADDR_ENABLE (1UL << 0)
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/* MTE tag check fault modes */
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# define PR_MTE_TCF_NONE 0UL
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# define PR_MTE_TCF_SYNC (1UL << 1)
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# define PR_MTE_TCF_ASYNC (1UL << 2)
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# define PR_MTE_TCF_MASK (PR_MTE_TCF_SYNC | PR_MTE_TCF_ASYNC)
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/* MTE tag inclusion mask */
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# define PR_MTE_TAG_SHIFT 3
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# define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT)
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/* Unused; kept only for source compatibility */
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# define PR_MTE_TCF_SHIFT 1
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/* MTE tag check store only */
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# define PR_MTE_STORE_ONLY (1UL << 19)
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/* RISC-V pointer masking tag length */
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# define PR_PMLEN_SHIFT 24
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# define PR_PMLEN_MASK (0x7fUL << PR_PMLEN_SHIFT)
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/* Control reclaim behavior when allocating memory */
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#define PR_SET_IO_FLUSHER 57
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#define PR_GET_IO_FLUSHER 58
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/* Dispatch syscalls to a userspace handler */
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#define PR_SET_SYSCALL_USER_DISPATCH 59
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# define PR_SYS_DISPATCH_OFF 0
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/* Enable dispatch except for the specified range */
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# define PR_SYS_DISPATCH_EXCLUSIVE_ON 1
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/* Enable dispatch for the specified range */
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# define PR_SYS_DISPATCH_INCLUSIVE_ON 2
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/* Legacy name for backwards compatibility */
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# define PR_SYS_DISPATCH_ON PR_SYS_DISPATCH_EXCLUSIVE_ON
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/* The control values for the user space selector when dispatch is enabled */
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# define SYSCALL_DISPATCH_FILTER_ALLOW 0
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# define SYSCALL_DISPATCH_FILTER_BLOCK 1
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/* Set/get enabled arm64 pointer authentication keys */
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#define PR_PAC_SET_ENABLED_KEYS 60
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#define PR_PAC_GET_ENABLED_KEYS 61
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/* Request the scheduler to share a core */
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#define PR_SCHED_CORE 62
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# define PR_SCHED_CORE_GET 0
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# define PR_SCHED_CORE_CREATE 1 /* create unique core_sched cookie */
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# define PR_SCHED_CORE_SHARE_TO 2 /* push core_sched cookie to pid */
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# define PR_SCHED_CORE_SHARE_FROM 3 /* pull core_sched cookie to pid */
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# define PR_SCHED_CORE_MAX 4
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# define PR_SCHED_CORE_SCOPE_THREAD 0
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# define PR_SCHED_CORE_SCOPE_THREAD_GROUP 1
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# define PR_SCHED_CORE_SCOPE_PROCESS_GROUP 2
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/* arm64 Scalable Matrix Extension controls */
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/* Flag values must be in sync with SVE versions */
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#define PR_SME_SET_VL 63 /* set task vector length */
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# define PR_SME_SET_VL_ONEXEC (1 << 18) /* defer effect until exec */
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#define PR_SME_GET_VL 64 /* get task vector length */
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/* Bits common to PR_SME_SET_VL and PR_SME_GET_VL */
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# define PR_SME_VL_LEN_MASK 0xffff
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# define PR_SME_VL_INHERIT (1 << 17) /* inherit across exec */
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/* Memory deny write / execute */
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#define PR_SET_MDWE 65
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# define PR_MDWE_REFUSE_EXEC_GAIN (1UL << 0)
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# define PR_MDWE_NO_INHERIT (1UL << 1)
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#define PR_GET_MDWE 66
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#define PR_SET_VMA 0x53564d41
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# define PR_SET_VMA_ANON_NAME 0
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#define PR_GET_AUXV 0x41555856
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#define PR_SET_MEMORY_MERGE 67
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#define PR_GET_MEMORY_MERGE 68
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#define PR_RISCV_V_SET_CONTROL 69
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#define PR_RISCV_V_GET_CONTROL 70
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# define PR_RISCV_V_VSTATE_CTRL_DEFAULT 0
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# define PR_RISCV_V_VSTATE_CTRL_OFF 1
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# define PR_RISCV_V_VSTATE_CTRL_ON 2
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# define PR_RISCV_V_VSTATE_CTRL_INHERIT (1 << 4)
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# define PR_RISCV_V_VSTATE_CTRL_CUR_MASK 0x3
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# define PR_RISCV_V_VSTATE_CTRL_NEXT_MASK 0xc
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# define PR_RISCV_V_VSTATE_CTRL_MASK 0x1f
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#define PR_RISCV_SET_ICACHE_FLUSH_CTX 71
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# define PR_RISCV_CTX_SW_FENCEI_ON 0
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# define PR_RISCV_CTX_SW_FENCEI_OFF 1
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# define PR_RISCV_SCOPE_PER_PROCESS 0
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# define PR_RISCV_SCOPE_PER_THREAD 1
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/* PowerPC Dynamic Execution Control Register (DEXCR) controls */
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#define PR_PPC_GET_DEXCR 72
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#define PR_PPC_SET_DEXCR 73
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/* DEXCR aspect to act on */
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# define PR_PPC_DEXCR_SBHE 0 /* Speculative branch hint enable */
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# define PR_PPC_DEXCR_IBRTPD 1 /* Indirect branch recurrent target prediction disable */
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# define PR_PPC_DEXCR_SRAPD 2 /* Subroutine return address prediction disable */
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# define PR_PPC_DEXCR_NPHIE 3 /* Non-privileged hash instruction enable */
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/* Action to apply / return */
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# define PR_PPC_DEXCR_CTRL_EDITABLE 0x1 /* Aspect can be modified with PR_PPC_SET_DEXCR */
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# define PR_PPC_DEXCR_CTRL_SET 0x2 /* Set the aspect for this process */
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# define PR_PPC_DEXCR_CTRL_CLEAR 0x4 /* Clear the aspect for this process */
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# define PR_PPC_DEXCR_CTRL_SET_ONEXEC 0x8 /* Set the aspect on exec */
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# define PR_PPC_DEXCR_CTRL_CLEAR_ONEXEC 0x10 /* Clear the aspect on exec */
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# define PR_PPC_DEXCR_CTRL_MASK 0x1f
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/*
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* Get the current shadow stack configuration for the current thread,
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* this will be the value configured via PR_SET_SHADOW_STACK_STATUS.
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*/
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#define PR_GET_SHADOW_STACK_STATUS 74
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/*
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* Set the current shadow stack configuration. Enabling the shadow
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* stack will cause a shadow stack to be allocated for the thread.
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*/
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#define PR_SET_SHADOW_STACK_STATUS 75
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# define PR_SHADOW_STACK_ENABLE (1UL << 0)
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# define PR_SHADOW_STACK_WRITE (1UL << 1)
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# define PR_SHADOW_STACK_PUSH (1UL << 2)
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/*
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* Prevent further changes to the specified shadow stack
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* configuration. All bits may be locked via this call, including
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* undefined bits.
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*/
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#define PR_LOCK_SHADOW_STACK_STATUS 76
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/*
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* Controls the mode of timer_create() for CRIU restore operations.
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* Enabling this allows CRIU to restore timers with explicit IDs.
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*
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* Don't use for normal operations as the result might be undefined.
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*/
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#define PR_TIMER_CREATE_RESTORE_IDS 77
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# define PR_TIMER_CREATE_RESTORE_IDS_OFF 0
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# define PR_TIMER_CREATE_RESTORE_IDS_ON 1
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# define PR_TIMER_CREATE_RESTORE_IDS_GET 2
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/* FUTEX hash management */
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#define PR_FUTEX_HASH 78
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# define PR_FUTEX_HASH_SET_SLOTS 1
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# define PR_FUTEX_HASH_GET_SLOTS 2
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#endif /* _LINUX_PRCTL_H */
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