Linus Torvalds cbbf0a759f * MTD changes: ... Apart from a binding conversion to yaml, only minor changes/small fixes have been merged. * Raw NAND changes: Various controller drivers received minor fixes like DMA mapping checks, better timing derivations or bitflip statistics. It has also been discovered that some Hynix NAND flashes were not supporting read-retries, which is not properly supported. * SPI NAND changes: In order to support high-speed modes, certain chips need extra configuration like adding more dummy cycles. This is now possible, especially on Winbond chips. Aside from that, Gigadevice gets support for a new chip (GD5F1GM9). * SPI NOR changes: A notable changes is the fix for exiting 4-byte addressing on Infineon SEMPER flashes. These flashes do not support the standard EX4B opcode (E9h), and use a vendor-specific opcode (B8h) instead. There is also a fix for unlocking flashes that are write-protected at power-on. This was caused by using an uninitialized mtd_info in spi_nor_try_unlock_all(). -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEE9HuaYnbmDhq/XIDIJWrqGEe9VoQFAmiLn/sACgkQJWrqGEe9 VoTGowf/c6kynDuMlQbTANv/UIYX/LRFZsnIx0LB32LWrhLaUIBsbFxejyt07WG9 ryej+xRUtSHGsqMIw+B/PjvA4hUNLdsSwO/udIwstXNQjJcO9OKp/ucpvlxLzIha REq8IifvT9vLLA+Efoq2L25dM14KjuFCAjwm3GH/SmdTOqPhI/Bbnx4vRWIPeXrx XZ69ovIiu5NqLTD5IFGsu+omhbFWlDtVALtKNknrTOXWrjLZhDpieO4f7M9rvru6 OwazFQAWuixzqZRMFqvOzu8KUDnOHi9gHrzi6tS7T1zBUDz9ywdBtaHYCd7VlMJh uV1wjUdWjnIh9E8R/llv3D+ko1Ya1w== =IS/d -----END PGP SIGNATURE----- Merge tag 'mtd/for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull mtd updates from Miquel Raynal: "MTD changes: - Apart from a binding conversion to yaml, only minor changes/small fixes have been merged. Raw NAND changes: - Minor fixes for various controller drivers like DMA mapping checks, better timing derivations or bitflip statistics. - some Hynix NAND flashes were not supporting read-retries, so don't even try to do it SPI NAND changes: - In order to support high-speed modes, certain chips need extra configuration like adding more dummy cycles. This is now possible, especially on Winbond chips. - Aside from that, Gigadevice gets support for a new chip (GD5F1GM9). SPI NOR changes: - A notable changes is the fix for exiting 4-byte addressing on Infineon SEMPER flashes. These flashes do not support the standard EX4B opcode (E9h), and use a vendor-specific opcode (B8h) instead. - There is also a fix for unlocking flashes that are write-protected at power-on. This was caused by using an uninitialized mtd_info in spi_nor_try_unlock_all()" * tag 'mtd/for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (26 commits) mtd: spinand: winbond: Add comment about the maximum frequency mtd: spinand: winbond: Enable high-speed modes on w35n0xjw mtd: spinand: winbond: Enable high-speed modes on w25n0xjw mtd: spinand: Add a ->configure_chip() hook mtd: spinand: Add a frequency field to all READ_FROM_CACHE variants mtd: spinand: Fix macro alignment spi: spi-mem: Take into account the actual maximum frequency spi: spi-mem: Use picoseconds for calculating the op durations mtd: rawnand: atmel: set pmecc data setup time mtd: spinand: propagate spinand_wait() errors from spinand_write_page() mtd: rawnand: fsmc: Add missing check after DMA map mtd: rawnand: rockchip: Add missing check after DMA map mtd: rawnand: hynix: don't try read-retry on SLC NANDs mtd: rawnand: atmel: Fix dma_mapping_error() address mtd: nand: brcmnand: fix mtd corrected bits stat mtd: rawnand: renesas: Add missing check after DMA map mtd: spinand: gigadevice: Add support for GD5F1GM9 chips mtd: nand: brcmnand: replace manual string choices with standard helpers mtd: map: Don't use "proxy" headers mtd: spi-nor: Fix spi_nor_try_unlock_all() ...		2025-07-31 13:43:02 -07:00
..
offload	spi: offload: types: include linux/bits.h	2025-02-11 13:15:28 +00:00
ad7877.h
ads7846.h
altera.h
at73c213.h
corgi_lcd.h
ds1305.h
eeprom.h
flash.h
libertas_spi.h
max7301.h
mc33880.h
mmc_spi.h
mxs-spi.h
sh_hspi.h
sh_msiof.h	spi: sh-msiof: Move register definitions to <linux/spi/sh_msiof.h>	2025-05-19 11:55:37 +01:00
spi_bitbang.h
spi_gpio.h
spi_oc_tiny.h
spi-fsl-dspi.h
spi-mem.h	spi: spi-mem: Take into account the actual maximum frequency	2025-07-30 11:32:05 +02:00
spi.h	spi: Raise limit on number of chip selects to 24	2025-06-29 22:10:52 +01:00
tdo24m.h
tle62x0.h
xilinx_spi.h