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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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6edf3152bd
Instead of an odd comment, cite the documentation, which says more clearly what's going on with the programming flow on some of the Intel SoCs. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
61 lines
2.3 KiB
C
61 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Intel Low Power Subsystem PWM controller driver */
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#ifndef __PLATFORM_DATA_X86_PWM_LPSS_H
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#define __PLATFORM_DATA_X86_PWM_LPSS_H
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#include <linux/types.h>
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struct device;
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struct pwm_lpss_chip;
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struct pwm_lpss_boardinfo {
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unsigned long clk_rate;
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unsigned int npwm;
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unsigned long base_unit_bits;
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/*
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* NOTE:
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* Intel Broxton, Apollo Lake, and Gemini Lake have different programming flow.
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*
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* Initial Enable or First Activation
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* 1. Program the base unit and on time divisor values.
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* 2. Set the software update bit.
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* 3. Poll in a loop on the PWMCTRL bit until software update bit is cleared.+
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* 4. Enable the PWM output by setting PWM Enable.
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* 5. Repeat the above steps for the next PWM Module.
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*
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* Dynamic update while PWM is Enabled
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* 1. Program the base unit and on-time divisor values.
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* 2. Set the software update bit.
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* 3. Repeat the above steps for the next PWM module.
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*
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* + After setting PWMCTRL register's SW update bit, hardware automatically
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* deasserts the SW update bit after a brief delay. It was observed that
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* setting of PWM enable is typically done via read-modify-write of the PWMCTRL
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* register. If there is no/little delay between setting software update bit
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* and setting enable bit via read-modify-write, it is possible that the read
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* could return with software enable as 1. In that case, the last write to set
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* enable to 1 could also set sw_update to 1. If this happens, sw_update gets
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* stuck and the driver code can hang as it explicitly waits for sw_update bit
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* to be 0 after setting the enable bit to 1. To avoid this race condition,
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* SW should poll on the software update bit to make sure that it is 0 before
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* doing the read-modify-write to set the enable bit to 1.
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*
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* Also, we noted that if sw_update bit was set in step #1 above then when it
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* is set again in step #2, sw_update bit never gets cleared and the flow hangs.
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* As such, we need to make sure that sw_update bit is 0 when doing step #1.
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*/
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bool bypass;
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/*
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* On some devices the _PS0/_PS3 AML code of the GPU (GFX0) device
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* messes with the PWM0 controllers state,
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*/
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bool other_devices_aml_touches_pwm_regs;
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};
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struct pwm_chip *devm_pwm_lpss_probe(struct device *dev, void __iomem *base,
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const struct pwm_lpss_boardinfo *info);
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#endif /* __PLATFORM_DATA_X86_PWM_LPSS_H */
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