mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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d1c696dba1
This common library will be used as a placeholder for helper functions shared by the host controller drivers. This avoids placing the host controller drivers specific helpers in drivers/pci/*.c, to avoid enlarging the kernel image on platforms that do not use host controller drivers at all (like x86/ACPI platforms). Suggested-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Link: https://patch.msgid.link/20250508-pcie-reset-slot-v4-3-7050093e2b50@linaro.org
97 lines
3.2 KiB
C
97 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2016 Broadcom
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*/
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#ifndef DRIVERS_PCI_ECAM_H
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#define DRIVERS_PCI_ECAM_H
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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/*
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* Memory address shift values for the byte-level address that
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* can be used when accessing the PCI Express Configuration Space.
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*/
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/*
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* Enhanced Configuration Access Mechanism (ECAM)
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*
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* See PCI Express Base Specification, Revision 5.0, Version 1.0,
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* Section 7.2.2, Table 7-1, p. 677.
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*/
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#define PCIE_ECAM_BUS_SHIFT 20 /* Bus number */
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#define PCIE_ECAM_DEVFN_SHIFT 12 /* Device and Function number */
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#define PCIE_ECAM_BUS_MASK 0xff
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#define PCIE_ECAM_DEVFN_MASK 0xff
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#define PCIE_ECAM_REG_MASK 0xfff /* Limit offset to a maximum of 4K */
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#define PCIE_ECAM_BUS(x) (((x) & PCIE_ECAM_BUS_MASK) << PCIE_ECAM_BUS_SHIFT)
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#define PCIE_ECAM_DEVFN(x) (((x) & PCIE_ECAM_DEVFN_MASK) << PCIE_ECAM_DEVFN_SHIFT)
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#define PCIE_ECAM_REG(x) ((x) & PCIE_ECAM_REG_MASK)
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#define PCIE_ECAM_OFFSET(bus, devfn, where) \
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(PCIE_ECAM_BUS(bus) | \
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PCIE_ECAM_DEVFN(devfn) | \
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PCIE_ECAM_REG(where))
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/*
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* struct to hold pci ops and bus shift of the config window
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* for a PCI controller.
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*/
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struct pci_config_window;
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struct pci_ecam_ops {
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unsigned int bus_shift;
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struct pci_ops pci_ops;
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int (*init)(struct pci_config_window *);
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int (*enable_device)(struct pci_host_bridge *,
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struct pci_dev *);
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void (*disable_device)(struct pci_host_bridge *,
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struct pci_dev *);
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};
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/*
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* struct to hold the mappings of a config space window. This
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* is expected to be used as sysdata for PCI controllers that
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* use ECAM.
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*/
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struct pci_config_window {
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struct resource res;
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struct resource busr;
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unsigned int bus_shift;
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void *priv;
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const struct pci_ecam_ops *ops;
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union {
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void __iomem *win; /* 64-bit single mapping */
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void __iomem **winp; /* 32-bit per-bus mapping */
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};
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struct device *parent;/* ECAM res was from this dev */
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};
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/* create and free pci_config_window */
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struct pci_config_window *pci_ecam_create(struct device *dev,
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struct resource *cfgres, struct resource *busr,
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const struct pci_ecam_ops *ops);
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void pci_ecam_free(struct pci_config_window *cfg);
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/* map_bus when ->sysdata is an instance of pci_config_window */
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void __iomem *pci_ecam_map_bus(struct pci_bus *bus, unsigned int devfn,
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int where);
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/* default ECAM ops */
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extern const struct pci_ecam_ops pci_generic_ecam_ops;
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#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
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extern const struct pci_ecam_ops pci_32b_ops; /* 32-bit accesses only */
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extern const struct pci_ecam_ops pci_32b_read_ops; /* 32-bit read only */
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extern const struct pci_ecam_ops hisi_pcie_ops; /* HiSilicon */
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extern const struct pci_ecam_ops thunder_pem_ecam_ops; /* Cavium ThunderX 1.x & 2.x */
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extern const struct pci_ecam_ops pci_thunder_ecam_ops; /* Cavium ThunderX 1.x */
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extern const struct pci_ecam_ops xgene_v1_pcie_ecam_ops; /* APM X-Gene PCIe v1 */
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extern const struct pci_ecam_ops xgene_v2_pcie_ecam_ops; /* APM X-Gene PCIe v2.x */
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extern const struct pci_ecam_ops al_pcie_ops; /* Amazon Annapurna Labs PCIe */
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extern const struct pci_ecam_ops tegra194_pcie_ops; /* Tegra194 PCIe */
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extern const struct pci_ecam_ops loongson_pci_ecam_ops; /* Loongson PCIe */
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#endif
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#endif
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