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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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4f8ceb0302
Add support for STM32MP25 SoC. A new hardware configuration register (HWCFGR2) has been added, to gather number of capture/compare channels, autonomous mode and input capture capability. The full feature set is implemented in LPTIM1/2/3/4. LPTIM5 supports a smaller set of features. This can now be read from HWCFGR registers. Add new registers to the stm32-lptimer.h: CCMR1, CCR2, HWCFGR1/2 and VERR. Update the stm32_lptimer data struct so signal the number of capture/compare channels to the child devices. Also Remove some unused bit masks (CMPOK_ARROK / CMPOKCF_ARROKCF). Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com> Link: https://lore.kernel.org/r/20250429125133.1574167-3-fabrice.gasnier@foss.st.com Signed-off-by: Lee Jones <lee@kernel.org>
100 lines
3.3 KiB
C
100 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* STM32 Low-Power Timer parent driver.
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* Copyright (C) STMicroelectronics 2017
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* Author: Fabrice Gasnier <fabrice.gasnier@st.com>
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* Inspired by Benjamin Gaignard's stm32-timers driver
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*/
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#ifndef _LINUX_STM32_LPTIMER_H_
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#define _LINUX_STM32_LPTIMER_H_
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#include <linux/clk.h>
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#include <linux/regmap.h>
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#define STM32_LPTIM_ISR 0x00 /* Interrupt and Status Reg */
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#define STM32_LPTIM_ICR 0x04 /* Interrupt Clear Reg */
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#define STM32_LPTIM_IER 0x08 /* Interrupt Enable Reg */
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#define STM32_LPTIM_CFGR 0x0C /* Configuration Reg */
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#define STM32_LPTIM_CR 0x10 /* Control Reg */
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#define STM32_LPTIM_CMP 0x14 /* Compare Reg (MP25 CCR1) */
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#define STM32_LPTIM_ARR 0x18 /* Autoreload Reg */
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#define STM32_LPTIM_CNT 0x1C /* Counter Reg */
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#define STM32_LPTIM_CCMR1 0x2C /* Capture/Compare Mode MP25 */
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#define STM32_LPTIM_CCR2 0x34 /* Compare Reg2 MP25 */
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#define STM32_LPTIM_HWCFGR2 0x3EC /* Hardware configuration register 2 - MP25 */
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#define STM32_LPTIM_HWCFGR1 0x3F0 /* Hardware configuration register 1 - MP15 */
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#define STM32_LPTIM_VERR 0x3F4 /* Version identification register - MP15 */
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/* STM32_LPTIM_ISR - bit fields */
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#define STM32_LPTIM_DIEROK_ARROK (BIT(24) | BIT(4)) /* MP25 */
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#define STM32_LPTIM_CMP2_ARROK (BIT(19) | BIT(4))
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#define STM32_LPTIM_CMPOK_ARROK GENMASK(4, 3)
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#define STM32_LPTIM_ARROK BIT(4)
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#define STM32_LPTIM_CMPOK BIT(3)
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/* STM32_LPTIM_ICR - bit fields */
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#define STM32_LPTIM_DIEROKCF_ARROKCF (BIT(24) | BIT(4)) /* MP25 */
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#define STM32_LPTIM_CMP2OKCF_ARROKCF (BIT(19) | BIT(4))
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#define STM32_LPTIM_CMPOKCF_ARROKCF GENMASK(4, 3)
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#define STM32_LPTIM_ARRMCF BIT(1)
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/* STM32_LPTIM_IER - bit fields */
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#define STM32_LPTIM_ARRMIE BIT(1)
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/* STM32_LPTIM_CR - bit fields */
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#define STM32_LPTIM_CNTSTRT BIT(2)
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#define STM32_LPTIM_SNGSTRT BIT(1)
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#define STM32_LPTIM_ENABLE BIT(0)
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/* STM32_LPTIM_CFGR - bit fields */
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#define STM32_LPTIM_ENC BIT(24)
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#define STM32_LPTIM_COUNTMODE BIT(23)
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#define STM32_LPTIM_WAVPOL BIT(21)
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#define STM32_LPTIM_PRESC GENMASK(11, 9)
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#define STM32_LPTIM_CKPOL GENMASK(2, 1)
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/* STM32_LPTIM_CKPOL */
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#define STM32_LPTIM_CKPOL_RISING_EDGE 0
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#define STM32_LPTIM_CKPOL_FALLING_EDGE 1
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#define STM32_LPTIM_CKPOL_BOTH_EDGES 2
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/* STM32_LPTIM_ARR */
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#define STM32_LPTIM_MAX_ARR 0xFFFF
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/* STM32_LPTIM_CCMR1 */
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#define STM32_LPTIM_CC2P GENMASK(19, 18)
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#define STM32_LPTIM_CC2E BIT(17)
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#define STM32_LPTIM_CC2SEL BIT(16)
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#define STM32_LPTIM_CC1P GENMASK(3, 2)
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#define STM32_LPTIM_CC1E BIT(1)
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#define STM32_LPTIM_CC1SEL BIT(0)
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/* STM32_LPTIM_HWCFGR1 */
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#define STM32_LPTIM_HWCFGR1_ENCODER BIT(16)
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/* STM32_LPTIM_HWCFGR2 */
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#define STM32_LPTIM_HWCFGR2_CHAN_NUM GENMASK(3, 0)
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/* STM32_LPTIM_VERR */
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#define STM32_LPTIM_VERR_23 0x23 /* STM32MP25 */
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/**
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* struct stm32_lptimer - STM32 Low-Power Timer data assigned by parent device
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* @clk: clock reference for this instance
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* @regmap: register map reference for this instance
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* @has_encoder: indicates this Low-Power Timer supports encoder mode
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* @num_cc_chans: indicates the number of capture/compare channels
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* @version: indicates the major and minor revision of the controller
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*/
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struct stm32_lptimer {
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struct clk *clk;
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struct regmap *regmap;
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bool has_encoder;
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unsigned int num_cc_chans;
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u32 version;
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};
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#endif
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