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5338709089
Add support for Samsung's S2MPG10 PMIC, which is a Power Management IC for mobile applications with buck converters, various LDOs, power meters, RTC, clock outputs, and additional GPIOs interfaces. Contrary to existing Samsung S2M series PMICs supported, communication is not via I2C, but via the Samsung ACPM firmware. This commit adds the core driver. Signed-off-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20250409-s2mpg10-v4-9-d66d5f39b6bf@linaro.org Signed-off-by: Lee Jones <lee@kernel.org>
345 lines
8.5 KiB
C
345 lines
8.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd
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* http://www.samsung.com
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*/
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#ifndef __LINUX_MFD_SEC_IRQ_H
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#define __LINUX_MFD_SEC_IRQ_H
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enum s2mpa01_irq {
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S2MPA01_IRQ_PWRONF,
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S2MPA01_IRQ_PWRONR,
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S2MPA01_IRQ_JIGONBF,
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S2MPA01_IRQ_JIGONBR,
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S2MPA01_IRQ_ACOKBF,
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S2MPA01_IRQ_ACOKBR,
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S2MPA01_IRQ_PWRON1S,
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S2MPA01_IRQ_MRB,
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S2MPA01_IRQ_RTC60S,
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S2MPA01_IRQ_RTCA1,
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S2MPA01_IRQ_RTCA0,
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S2MPA01_IRQ_SMPL,
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S2MPA01_IRQ_RTC1S,
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S2MPA01_IRQ_WTSR,
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S2MPA01_IRQ_INT120C,
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S2MPA01_IRQ_INT140C,
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S2MPA01_IRQ_LDO3_TSD,
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S2MPA01_IRQ_B16_TSD,
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S2MPA01_IRQ_B24_TSD,
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S2MPA01_IRQ_B35_TSD,
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S2MPA01_IRQ_NR,
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};
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#define S2MPA01_IRQ_PWRONF_MASK (1 << 0)
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#define S2MPA01_IRQ_PWRONR_MASK (1 << 1)
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#define S2MPA01_IRQ_JIGONBF_MASK (1 << 2)
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#define S2MPA01_IRQ_JIGONBR_MASK (1 << 3)
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#define S2MPA01_IRQ_ACOKBF_MASK (1 << 4)
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#define S2MPA01_IRQ_ACOKBR_MASK (1 << 5)
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#define S2MPA01_IRQ_PWRON1S_MASK (1 << 6)
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#define S2MPA01_IRQ_MRB_MASK (1 << 7)
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#define S2MPA01_IRQ_RTC60S_MASK (1 << 0)
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#define S2MPA01_IRQ_RTCA1_MASK (1 << 1)
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#define S2MPA01_IRQ_RTCA0_MASK (1 << 2)
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#define S2MPA01_IRQ_SMPL_MASK (1 << 3)
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#define S2MPA01_IRQ_RTC1S_MASK (1 << 4)
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#define S2MPA01_IRQ_WTSR_MASK (1 << 5)
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#define S2MPA01_IRQ_INT120C_MASK (1 << 0)
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#define S2MPA01_IRQ_INT140C_MASK (1 << 1)
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#define S2MPA01_IRQ_LDO3_TSD_MASK (1 << 2)
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#define S2MPA01_IRQ_B16_TSD_MASK (1 << 3)
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#define S2MPA01_IRQ_B24_TSD_MASK (1 << 4)
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#define S2MPA01_IRQ_B35_TSD_MASK (1 << 5)
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enum s2mpg10_irq {
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/* PMIC */
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S2MPG10_IRQ_PWRONF,
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S2MPG10_IRQ_PWRONR,
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S2MPG10_IRQ_JIGONBF,
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S2MPG10_IRQ_JIGONBR,
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S2MPG10_IRQ_ACOKBF,
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S2MPG10_IRQ_ACOKBR,
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S2MPG10_IRQ_PWRON1S,
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S2MPG10_IRQ_MRB,
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#define S2MPG10_IRQ_PWRONF_MASK BIT(0)
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#define S2MPG10_IRQ_PWRONR_MASK BIT(1)
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#define S2MPG10_IRQ_JIGONBF_MASK BIT(2)
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#define S2MPG10_IRQ_JIGONBR_MASK BIT(3)
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#define S2MPG10_IRQ_ACOKBF_MASK BIT(4)
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#define S2MPG10_IRQ_ACOKBR_MASK BIT(5)
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#define S2MPG10_IRQ_PWRON1S_MASK BIT(6)
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#define S2MPG10_IRQ_MRB_MASK BIT(7)
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S2MPG10_IRQ_RTC60S,
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S2MPG10_IRQ_RTCA1,
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S2MPG10_IRQ_RTCA0,
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S2MPG10_IRQ_RTC1S,
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S2MPG10_IRQ_WTSR_COLDRST,
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S2MPG10_IRQ_WTSR,
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S2MPG10_IRQ_WRST,
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S2MPG10_IRQ_SMPL,
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#define S2MPG10_IRQ_RTC60S_MASK BIT(0)
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#define S2MPG10_IRQ_RTCA1_MASK BIT(1)
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#define S2MPG10_IRQ_RTCA0_MASK BIT(2)
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#define S2MPG10_IRQ_RTC1S_MASK BIT(3)
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#define S2MPG10_IRQ_WTSR_COLDRST_MASK BIT(4)
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#define S2MPG10_IRQ_WTSR_MASK BIT(5)
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#define S2MPG10_IRQ_WRST_MASK BIT(6)
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#define S2MPG10_IRQ_SMPL_MASK BIT(7)
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S2MPG10_IRQ_120C,
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S2MPG10_IRQ_140C,
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S2MPG10_IRQ_TSD,
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S2MPG10_IRQ_PIF_TIMEOUT1,
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S2MPG10_IRQ_PIF_TIMEOUT2,
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S2MPG10_IRQ_SPD_PARITY_ERR,
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S2MPG10_IRQ_SPD_ABNORMAL_STOP,
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S2MPG10_IRQ_PMETER_OVERF,
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#define S2MPG10_IRQ_INT120C_MASK BIT(0)
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#define S2MPG10_IRQ_INT140C_MASK BIT(1)
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#define S2MPG10_IRQ_TSD_MASK BIT(2)
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#define S2MPG10_IRQ_PIF_TIMEOUT1_MASK BIT(3)
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#define S2MPG10_IRQ_PIF_TIMEOUT2_MASK BIT(4)
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#define S2MPG10_IRQ_SPD_PARITY_ERR_MASK BIT(5)
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#define S2MPG10_IRQ_SPD_ABNORMAL_STOP_MASK BIT(6)
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#define S2MPG10_IRQ_PMETER_OVERF_MASK BIT(7)
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S2MPG10_IRQ_OCP_B1M,
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S2MPG10_IRQ_OCP_B2M,
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S2MPG10_IRQ_OCP_B3M,
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S2MPG10_IRQ_OCP_B4M,
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S2MPG10_IRQ_OCP_B5M,
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S2MPG10_IRQ_OCP_B6M,
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S2MPG10_IRQ_OCP_B7M,
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S2MPG10_IRQ_OCP_B8M,
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#define S2MPG10_IRQ_OCP_B1M_MASK BIT(0)
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#define S2MPG10_IRQ_OCP_B2M_MASK BIT(1)
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#define S2MPG10_IRQ_OCP_B3M_MASK BIT(2)
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#define S2MPG10_IRQ_OCP_B4M_MASK BIT(3)
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#define S2MPG10_IRQ_OCP_B5M_MASK BIT(4)
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#define S2MPG10_IRQ_OCP_B6M_MASK BIT(5)
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#define S2MPG10_IRQ_OCP_B7M_MASK BIT(6)
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#define S2MPG10_IRQ_OCP_B8M_MASK BIT(7)
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S2MPG10_IRQ_OCP_B9M,
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S2MPG10_IRQ_OCP_B10M,
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S2MPG10_IRQ_WLWP_ACC,
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S2MPG10_IRQ_SMPL_TIMEOUT,
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S2MPG10_IRQ_WTSR_TIMEOUT,
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S2MPG10_IRQ_SPD_SRP_PKT_RST,
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#define S2MPG10_IRQ_OCP_B9M_MASK BIT(0)
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#define S2MPG10_IRQ_OCP_B10M_MASK BIT(1)
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#define S2MPG10_IRQ_WLWP_ACC_MASK BIT(2)
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#define S2MPG10_IRQ_SMPL_TIMEOUT_MASK BIT(5)
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#define S2MPG10_IRQ_WTSR_TIMEOUT_MASK BIT(6)
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#define S2MPG10_IRQ_SPD_SRP_PKT_RST_MASK BIT(7)
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S2MPG10_IRQ_PWR_WARN_CH0,
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S2MPG10_IRQ_PWR_WARN_CH1,
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S2MPG10_IRQ_PWR_WARN_CH2,
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S2MPG10_IRQ_PWR_WARN_CH3,
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S2MPG10_IRQ_PWR_WARN_CH4,
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S2MPG10_IRQ_PWR_WARN_CH5,
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S2MPG10_IRQ_PWR_WARN_CH6,
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S2MPG10_IRQ_PWR_WARN_CH7,
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#define S2MPG10_IRQ_PWR_WARN_CH0_MASK BIT(0)
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#define S2MPG10_IRQ_PWR_WARN_CH1_MASK BIT(1)
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#define S2MPG10_IRQ_PWR_WARN_CH2_MASK BIT(2)
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#define S2MPG10_IRQ_PWR_WARN_CH3_MASK BIT(3)
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#define S2MPG10_IRQ_PWR_WARN_CH4_MASK BIT(4)
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#define S2MPG10_IRQ_PWR_WARN_CH5_MASK BIT(5)
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#define S2MPG10_IRQ_PWR_WARN_CH6_MASK BIT(6)
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#define S2MPG10_IRQ_PWR_WARN_CH7_MASK BIT(7)
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S2MPG10_IRQ_NR,
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};
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enum s2mps11_irq {
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S2MPS11_IRQ_PWRONF,
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S2MPS11_IRQ_PWRONR,
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S2MPS11_IRQ_JIGONBF,
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S2MPS11_IRQ_JIGONBR,
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S2MPS11_IRQ_ACOKBF,
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S2MPS11_IRQ_ACOKBR,
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S2MPS11_IRQ_PWRON1S,
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S2MPS11_IRQ_MRB,
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S2MPS11_IRQ_RTC60S,
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S2MPS11_IRQ_RTCA1,
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S2MPS11_IRQ_RTCA0,
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S2MPS11_IRQ_SMPL,
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S2MPS11_IRQ_RTC1S,
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S2MPS11_IRQ_WTSR,
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S2MPS11_IRQ_INT120C,
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S2MPS11_IRQ_INT140C,
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S2MPS11_IRQ_NR,
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};
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#define S2MPS11_IRQ_PWRONF_MASK (1 << 0)
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#define S2MPS11_IRQ_PWRONR_MASK (1 << 1)
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#define S2MPS11_IRQ_JIGONBF_MASK (1 << 2)
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#define S2MPS11_IRQ_JIGONBR_MASK (1 << 3)
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#define S2MPS11_IRQ_ACOKBF_MASK (1 << 4)
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#define S2MPS11_IRQ_ACOKBR_MASK (1 << 5)
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#define S2MPS11_IRQ_PWRON1S_MASK (1 << 6)
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#define S2MPS11_IRQ_MRB_MASK (1 << 7)
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#define S2MPS11_IRQ_RTC60S_MASK (1 << 0)
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#define S2MPS11_IRQ_RTCA1_MASK (1 << 1)
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#define S2MPS11_IRQ_RTCA0_MASK (1 << 2)
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#define S2MPS11_IRQ_SMPL_MASK (1 << 3)
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#define S2MPS11_IRQ_RTC1S_MASK (1 << 4)
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#define S2MPS11_IRQ_WTSR_MASK (1 << 5)
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#define S2MPS11_IRQ_INT120C_MASK (1 << 0)
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#define S2MPS11_IRQ_INT140C_MASK (1 << 1)
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enum s2mps14_irq {
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S2MPS14_IRQ_PWRONF,
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S2MPS14_IRQ_PWRONR,
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S2MPS14_IRQ_JIGONBF,
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S2MPS14_IRQ_JIGONBR,
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S2MPS14_IRQ_ACOKBF,
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S2MPS14_IRQ_ACOKBR,
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S2MPS14_IRQ_PWRON1S,
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S2MPS14_IRQ_MRB,
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S2MPS14_IRQ_RTC60S,
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S2MPS14_IRQ_RTCA1,
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S2MPS14_IRQ_RTCA0,
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S2MPS14_IRQ_SMPL,
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S2MPS14_IRQ_RTC1S,
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S2MPS14_IRQ_WTSR,
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S2MPS14_IRQ_INT120C,
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S2MPS14_IRQ_INT140C,
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S2MPS14_IRQ_TSD,
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S2MPS14_IRQ_NR,
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};
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enum s2mpu02_irq {
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S2MPU02_IRQ_PWRONF,
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S2MPU02_IRQ_PWRONR,
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S2MPU02_IRQ_JIGONBF,
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S2MPU02_IRQ_JIGONBR,
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S2MPU02_IRQ_ACOKBF,
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S2MPU02_IRQ_ACOKBR,
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S2MPU02_IRQ_PWRON1S,
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S2MPU02_IRQ_MRB,
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S2MPU02_IRQ_RTC60S,
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S2MPU02_IRQ_RTCA1,
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S2MPU02_IRQ_RTCA0,
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S2MPU02_IRQ_SMPL,
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S2MPU02_IRQ_RTC1S,
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S2MPU02_IRQ_WTSR,
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S2MPU02_IRQ_INT120C,
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S2MPU02_IRQ_INT140C,
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S2MPU02_IRQ_TSD,
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S2MPU02_IRQ_NR,
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};
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/* Masks for interrupts are the same as in s2mps11 */
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#define S2MPS14_IRQ_TSD_MASK (1 << 2)
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enum s2mpu05_irq {
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S2MPU05_IRQ_PWRONF,
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S2MPU05_IRQ_PWRONR,
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S2MPU05_IRQ_JIGONBF,
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S2MPU05_IRQ_JIGONBR,
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S2MPU05_IRQ_ACOKF,
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S2MPU05_IRQ_ACOKR,
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S2MPU05_IRQ_PWRON1S,
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S2MPU05_IRQ_MRB,
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S2MPU05_IRQ_RTC60S,
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S2MPU05_IRQ_RTCA1,
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S2MPU05_IRQ_RTCA0,
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S2MPU05_IRQ_SMPL,
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S2MPU05_IRQ_RTC1S,
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S2MPU05_IRQ_WTSR,
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S2MPU05_IRQ_INT120C,
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S2MPU05_IRQ_INT140C,
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S2MPU05_IRQ_TSD,
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S2MPU05_IRQ_NR,
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};
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#define S2MPU05_IRQ_PWRONF_MASK BIT(0)
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#define S2MPU05_IRQ_PWRONR_MASK BIT(1)
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#define S2MPU05_IRQ_JIGONBF_MASK BIT(2)
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#define S2MPU05_IRQ_JIGONBR_MASK BIT(3)
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#define S2MPU05_IRQ_ACOKF_MASK BIT(4)
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#define S2MPU05_IRQ_ACOKR_MASK BIT(5)
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#define S2MPU05_IRQ_PWRON1S_MASK BIT(6)
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#define S2MPU05_IRQ_MRB_MASK BIT(7)
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#define S2MPU05_IRQ_RTC60S_MASK BIT(0)
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#define S2MPU05_IRQ_RTCA1_MASK BIT(1)
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#define S2MPU05_IRQ_RTCA0_MASK BIT(2)
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#define S2MPU05_IRQ_SMPL_MASK BIT(3)
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#define S2MPU05_IRQ_RTC1S_MASK BIT(4)
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#define S2MPU05_IRQ_WTSR_MASK BIT(5)
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#define S2MPU05_IRQ_INT120C_MASK BIT(0)
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#define S2MPU05_IRQ_INT140C_MASK BIT(1)
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#define S2MPU05_IRQ_TSD_MASK BIT(2)
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enum s5m8767_irq {
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S5M8767_IRQ_PWRR,
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S5M8767_IRQ_PWRF,
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S5M8767_IRQ_PWR1S,
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S5M8767_IRQ_JIGR,
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S5M8767_IRQ_JIGF,
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S5M8767_IRQ_LOWBAT2,
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S5M8767_IRQ_LOWBAT1,
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S5M8767_IRQ_MRB,
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S5M8767_IRQ_DVSOK2,
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S5M8767_IRQ_DVSOK3,
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S5M8767_IRQ_DVSOK4,
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S5M8767_IRQ_RTC60S,
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S5M8767_IRQ_RTCA1,
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S5M8767_IRQ_RTCA2,
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S5M8767_IRQ_SMPL,
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S5M8767_IRQ_RTC1S,
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S5M8767_IRQ_WTSR,
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S5M8767_IRQ_NR,
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};
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#define S5M8767_IRQ_PWRR_MASK (1 << 0)
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#define S5M8767_IRQ_PWRF_MASK (1 << 1)
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#define S5M8767_IRQ_PWR1S_MASK (1 << 3)
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#define S5M8767_IRQ_JIGR_MASK (1 << 4)
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#define S5M8767_IRQ_JIGF_MASK (1 << 5)
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#define S5M8767_IRQ_LOWBAT2_MASK (1 << 6)
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#define S5M8767_IRQ_LOWBAT1_MASK (1 << 7)
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#define S5M8767_IRQ_MRB_MASK (1 << 2)
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#define S5M8767_IRQ_DVSOK2_MASK (1 << 3)
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#define S5M8767_IRQ_DVSOK3_MASK (1 << 4)
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#define S5M8767_IRQ_DVSOK4_MASK (1 << 5)
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#define S5M8767_IRQ_RTC60S_MASK (1 << 0)
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#define S5M8767_IRQ_RTCA1_MASK (1 << 1)
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#define S5M8767_IRQ_RTCA2_MASK (1 << 2)
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#define S5M8767_IRQ_SMPL_MASK (1 << 3)
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#define S5M8767_IRQ_RTC1S_MASK (1 << 4)
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#define S5M8767_IRQ_WTSR_MASK (1 << 5)
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#endif /* __LINUX_MFD_SEC_IRQ_H */
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