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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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4094040b1a
The ROHM BD96802 PMIC looks from software point of view a lot like ROHM BD96801 PMIC. Just with reduced number of voltage rails. Both PMICs provide two physical IRQ lines referred as INTB and ERRB and contain blocks implementing regulator controls and a weatchdog. Hence it makes sense to use same MFD core for both PMICs. Add support for ROHM BD96802 scalable companion PMIC to the BD96801 core driver. Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/05957d194425a79a4f35f287695c3d9ca2ed1ae2.1744090658.git.mazziesaccount@gmail.com Signed-off-by: Lee Jones <lee@kernel.org>
75 lines
1.8 KiB
C
75 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2025 ROHM Semiconductors
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*
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* The digital interface of trhe BD96802 PMIC is a reduced version of the
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* BD96801. Hence the BD96801 definitions are used for registers and masks
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* while this header only holds the IRQ definitions - mainly to avoid gaps in
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* IRQ numbers caused by the lack of some BUCKs / LDOs and their respective
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* IRQs.
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*/
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#ifndef __LINUX_MFD_BD96802_H__
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#define __LINUX_MFD_BD96802_H__
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/* ERRB IRQs */
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enum {
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/* Reg 0x52, 0x53, 0x54 - ERRB system IRQs */
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BD96802_OTP_ERR_STAT,
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BD96802_DBIST_ERR_STAT,
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BD96802_EEP_ERR_STAT,
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BD96802_ABIST_ERR_STAT,
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BD96802_PRSTB_ERR_STAT,
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BD96802_DRMOS1_ERR_STAT,
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BD96802_DRMOS2_ERR_STAT,
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BD96802_SLAVE_ERR_STAT,
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BD96802_VREF_ERR_STAT,
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BD96802_TSD_ERR_STAT,
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BD96802_UVLO_ERR_STAT,
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BD96802_OVLO_ERR_STAT,
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BD96802_OSC_ERR_STAT,
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BD96802_PON_ERR_STAT,
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BD96802_POFF_ERR_STAT,
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BD96802_CMD_SHDN_ERR_STAT,
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BD96802_INT_SHDN_ERR_STAT,
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/* Reg 0x55 BUCK1 ERR IRQs */
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BD96802_BUCK1_PVIN_ERR_STAT,
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BD96802_BUCK1_OVP_ERR_STAT,
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BD96802_BUCK1_UVP_ERR_STAT,
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BD96802_BUCK1_SHDN_ERR_STAT,
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/* Reg 0x56 BUCK2 ERR IRQs */
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BD96802_BUCK2_PVIN_ERR_STAT,
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BD96802_BUCK2_OVP_ERR_STAT,
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BD96802_BUCK2_UVP_ERR_STAT,
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BD96802_BUCK2_SHDN_ERR_STAT,
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};
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/* INTB IRQs */
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enum {
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/* Reg 0x5c (System INTB) */
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BD96802_TW_STAT,
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BD96802_WDT_ERR_STAT,
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BD96802_I2C_ERR_STAT,
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BD96802_CHIP_IF_ERR_STAT,
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/* Reg 0x5d (BUCK1 INTB) */
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BD96802_BUCK1_OCPH_STAT,
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BD96802_BUCK1_OCPL_STAT,
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BD96802_BUCK1_OCPN_STAT,
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BD96802_BUCK1_OVD_STAT,
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BD96802_BUCK1_UVD_STAT,
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BD96802_BUCK1_TW_CH_STAT,
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/* Reg 0x5e (BUCK2 INTB) */
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BD96802_BUCK2_OCPH_STAT,
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BD96802_BUCK2_OCPL_STAT,
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BD96802_BUCK2_OCPN_STAT,
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BD96802_BUCK2_OVD_STAT,
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BD96802_BUCK2_UVD_STAT,
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BD96802_BUCK2_TW_CH_STAT,
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};
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#endif
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