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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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4094040b1a
The ROHM BD96802 PMIC looks from software point of view a lot like ROHM BD96801 PMIC. Just with reduced number of voltage rails. Both PMICs provide two physical IRQ lines referred as INTB and ERRB and contain blocks implementing regulator controls and a weatchdog. Hence it makes sense to use same MFD core for both PMICs. Add support for ROHM BD96802 scalable companion PMIC to the BD96801 core driver. Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/05957d194425a79a4f35f287695c3d9ca2ed1ae2.1744090658.git.mazziesaccount@gmail.com Signed-off-by: Lee Jones <lee@kernel.org>
218 lines
5.8 KiB
C
218 lines
5.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/* Copyright (C) 2024 ROHM Semiconductors */
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#ifndef __MFD_BD96801_H__
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#define __MFD_BD96801_H__
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#define BD96801_REG_SSCG_CTRL 0x09
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#define BD96801_REG_SHD_INTB 0x20
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#define BD96801_LDO5_VOL_LVL_REG 0x2c
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#define BD96801_LDO6_VOL_LVL_REG 0x2d
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#define BD96801_LDO7_VOL_LVL_REG 0x2e
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#define BD96801_REG_BUCK_OVP 0x30
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#define BD96801_REG_BUCK_OVD 0x35
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#define BD96801_REG_LDO_OVP 0x31
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#define BD96801_REG_LDO_OVD 0x36
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#define BD96801_REG_BOOT_OVERTIME 0x3a
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#define BD96801_REG_WD_TMO 0x40
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#define BD96801_REG_WD_CONF 0x41
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#define BD96801_REG_WD_FEED 0x42
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#define BD96801_REG_WD_FAILCOUNT 0x43
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#define BD96801_REG_WD_ASK 0x46
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#define BD96801_REG_WD_STATUS 0x4a
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#define BD96801_REG_PMIC_STATE 0x4f
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#define BD96801_REG_EXT_STATE 0x50
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#define BD96801_STATE_STBY 0x09
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#define BD96801_LOCK_REG 0x04
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#define BD96801_UNLOCK 0x9d
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#define BD96801_LOCK 0x00
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/* IRQ register area */
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#define BD96801_REG_INT_MAIN 0x51
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/*
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* The BD96801 has two physical IRQ lines, INTB and ERRB.
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*
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* The 'main status register' is located at 0x51.
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* The ERRB status registers are located at 0x52 ... 0x5B
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* INTB status registers are at range 0x5c ... 0x63
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*/
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#define BD96801_REG_INT_SYS_ERRB1 0x52
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#define BD96801_REG_INT_BUCK2_ERRB 0x56
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#define BD96801_REG_INT_SYS_INTB 0x5c
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#define BD96801_REG_INT_BUCK2_INTB 0x5e
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#define BD96801_REG_INT_LDO7_INTB 0x63
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/* MASK registers */
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#define BD96801_REG_MASK_SYS_INTB 0x73
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#define BD96801_REG_MASK_SYS_ERRB 0x69
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#define BD96801_MAX_REGISTER 0x7a
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#define BD96801_OTP_ERR_MASK BIT(0)
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#define BD96801_DBIST_ERR_MASK BIT(1)
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#define BD96801_EEP_ERR_MASK BIT(2)
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#define BD96801_ABIST_ERR_MASK BIT(3)
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#define BD96801_PRSTB_ERR_MASK BIT(4)
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#define BD96801_DRMOS1_ERR_MASK BIT(5)
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#define BD96801_DRMOS2_ERR_MASK BIT(6)
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#define BD96801_SLAVE_ERR_MASK BIT(7)
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#define BD96801_VREF_ERR_MASK BIT(0)
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#define BD96801_TSD_ERR_MASK BIT(1)
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#define BD96801_UVLO_ERR_MASK BIT(2)
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#define BD96801_OVLO_ERR_MASK BIT(3)
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#define BD96801_OSC_ERR_MASK BIT(4)
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#define BD96801_PON_ERR_MASK BIT(5)
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#define BD96801_POFF_ERR_MASK BIT(6)
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#define BD96801_CMD_SHDN_ERR_MASK BIT(7)
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#define BD96801_INT_PRSTB_WDT_ERR_MASK BIT(0)
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#define BD96801_INT_CHIP_IF_ERR_MASK BIT(3)
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#define BD96801_INT_SHDN_ERR_MASK BIT(7)
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#define BD96801_OUT_PVIN_ERR_MASK BIT(0)
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#define BD96801_OUT_OVP_ERR_MASK BIT(1)
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#define BD96801_OUT_UVP_ERR_MASK BIT(2)
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#define BD96801_OUT_SHDN_ERR_MASK BIT(7)
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/* ERRB IRQs */
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enum {
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/* Reg 0x52, 0x53, 0x54 - ERRB system IRQs */
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BD96801_OTP_ERR_STAT,
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BD96801_DBIST_ERR_STAT,
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BD96801_EEP_ERR_STAT,
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BD96801_ABIST_ERR_STAT,
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BD96801_PRSTB_ERR_STAT,
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BD96801_DRMOS1_ERR_STAT,
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BD96801_DRMOS2_ERR_STAT,
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BD96801_SLAVE_ERR_STAT,
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BD96801_VREF_ERR_STAT,
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BD96801_TSD_ERR_STAT,
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BD96801_UVLO_ERR_STAT,
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BD96801_OVLO_ERR_STAT,
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BD96801_OSC_ERR_STAT,
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BD96801_PON_ERR_STAT,
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BD96801_POFF_ERR_STAT,
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BD96801_CMD_SHDN_ERR_STAT,
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BD96801_INT_PRSTB_WDT_ERR,
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BD96801_INT_CHIP_IF_ERR,
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BD96801_INT_SHDN_ERR_STAT,
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/* Reg 0x55 BUCK1 ERR IRQs */
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BD96801_BUCK1_PVIN_ERR_STAT,
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BD96801_BUCK1_OVP_ERR_STAT,
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BD96801_BUCK1_UVP_ERR_STAT,
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BD96801_BUCK1_SHDN_ERR_STAT,
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/* Reg 0x56 BUCK2 ERR IRQs */
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BD96801_BUCK2_PVIN_ERR_STAT,
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BD96801_BUCK2_OVP_ERR_STAT,
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BD96801_BUCK2_UVP_ERR_STAT,
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BD96801_BUCK2_SHDN_ERR_STAT,
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/* Reg 0x57 BUCK3 ERR IRQs */
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BD96801_BUCK3_PVIN_ERR_STAT,
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BD96801_BUCK3_OVP_ERR_STAT,
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BD96801_BUCK3_UVP_ERR_STAT,
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BD96801_BUCK3_SHDN_ERR_STAT,
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/* Reg 0x58 BUCK4 ERR IRQs */
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BD96801_BUCK4_PVIN_ERR_STAT,
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BD96801_BUCK4_OVP_ERR_STAT,
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BD96801_BUCK4_UVP_ERR_STAT,
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BD96801_BUCK4_SHDN_ERR_STAT,
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/* Reg 0x59 LDO5 ERR IRQs */
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BD96801_LDO5_PVIN_ERR_STAT,
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BD96801_LDO5_OVP_ERR_STAT,
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BD96801_LDO5_UVP_ERR_STAT,
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BD96801_LDO5_SHDN_ERR_STAT,
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/* Reg 0x5a LDO6 ERR IRQs */
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BD96801_LDO6_PVIN_ERR_STAT,
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BD96801_LDO6_OVP_ERR_STAT,
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BD96801_LDO6_UVP_ERR_STAT,
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BD96801_LDO6_SHDN_ERR_STAT,
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/* Reg 0x5b LDO7 ERR IRQs */
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BD96801_LDO7_PVIN_ERR_STAT,
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BD96801_LDO7_OVP_ERR_STAT,
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BD96801_LDO7_UVP_ERR_STAT,
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BD96801_LDO7_SHDN_ERR_STAT,
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};
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/* INTB IRQs */
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enum {
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/* Reg 0x5c (System INTB) */
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BD96801_TW_STAT,
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BD96801_WDT_ERR_STAT,
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BD96801_I2C_ERR_STAT,
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BD96801_CHIP_IF_ERR_STAT,
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/* Reg 0x5d (BUCK1 INTB) */
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BD96801_BUCK1_OCPH_STAT,
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BD96801_BUCK1_OCPL_STAT,
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BD96801_BUCK1_OCPN_STAT,
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BD96801_BUCK1_OVD_STAT,
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BD96801_BUCK1_UVD_STAT,
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BD96801_BUCK1_TW_CH_STAT,
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/* Reg 0x5e (BUCK2 INTB) */
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BD96801_BUCK2_OCPH_STAT,
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BD96801_BUCK2_OCPL_STAT,
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BD96801_BUCK2_OCPN_STAT,
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BD96801_BUCK2_OVD_STAT,
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BD96801_BUCK2_UVD_STAT,
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BD96801_BUCK2_TW_CH_STAT,
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/* Reg 0x5f (BUCK3 INTB)*/
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BD96801_BUCK3_OCPH_STAT,
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BD96801_BUCK3_OCPL_STAT,
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BD96801_BUCK3_OCPN_STAT,
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BD96801_BUCK3_OVD_STAT,
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BD96801_BUCK3_UVD_STAT,
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BD96801_BUCK3_TW_CH_STAT,
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/* Reg 0x60 (BUCK4 INTB)*/
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BD96801_BUCK4_OCPH_STAT,
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BD96801_BUCK4_OCPL_STAT,
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BD96801_BUCK4_OCPN_STAT,
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BD96801_BUCK4_OVD_STAT,
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BD96801_BUCK4_UVD_STAT,
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BD96801_BUCK4_TW_CH_STAT,
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/* Reg 0x61 (LDO5 INTB) */
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BD96801_LDO5_OCPH_STAT, /* bit [0] */
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BD96801_LDO5_OVD_STAT, /* bit [3] */
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BD96801_LDO5_UVD_STAT, /* bit [4] */
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/* Reg 0x62 (LDO6 INTB) */
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BD96801_LDO6_OCPH_STAT, /* bit [0] */
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BD96801_LDO6_OVD_STAT, /* bit [3] */
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BD96801_LDO6_UVD_STAT, /* bit [4] */
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/* Reg 0x63 (LDO7 INTB) */
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BD96801_LDO7_OCPH_STAT, /* bit [0] */
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BD96801_LDO7_OVD_STAT, /* bit [3] */
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BD96801_LDO7_UVD_STAT, /* bit [4] */
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};
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/* IRQ MASKs */
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#define BD96801_TW_STAT_MASK BIT(0)
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#define BD96801_WDT_ERR_STAT_MASK BIT(1)
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#define BD96801_I2C_ERR_STAT_MASK BIT(2)
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#define BD96801_CHIP_IF_ERR_STAT_MASK BIT(3)
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#define BD96801_BUCK_OCPH_STAT_MASK BIT(0)
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#define BD96801_BUCK_OCPL_STAT_MASK BIT(1)
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#define BD96801_BUCK_OCPN_STAT_MASK BIT(2)
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#define BD96801_BUCK_OVD_STAT_MASK BIT(3)
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#define BD96801_BUCK_UVD_STAT_MASK BIT(4)
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#define BD96801_BUCK_TW_CH_STAT_MASK BIT(5)
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#define BD96801_LDO_OCPH_STAT_MASK BIT(0)
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#define BD96801_LDO_OVD_STAT_MASK BIT(3)
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#define BD96801_LDO_UVD_STAT_MASK BIT(4)
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#endif
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