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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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The Samsung Exynos mailbox controller, used on Google GS101 SoC, has 16 flag bits for hardware interrupt generation and a shared register for passing mailbox messages. When the controller is used by the ACPM interface the shared register is ignored and the mailbox controller acts as a doorbell. The controller just raises the interrupt to APM after the ACPM interface has written the message to SRAM. Add support for the Samsung Exynos mailbox controller. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
20 lines
375 B
C
20 lines
375 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Exynos mailbox message.
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*
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* Copyright 2024 Linaro Ltd.
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*/
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#ifndef _LINUX_EXYNOS_MESSAGE_H_
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#define _LINUX_EXYNOS_MESSAGE_H_
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#define EXYNOS_MBOX_CHAN_TYPE_DOORBELL 0
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#define EXYNOS_MBOX_CHAN_TYPE_DATA 1
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struct exynos_mbox_msg {
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unsigned int chan_id;
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unsigned int chan_type;
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};
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#endif /* _LINUX_EXYNOS_MESSAGE_H_ */
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