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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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a1c940cbf5
Erase command is slow on discrete graphics storage and may overshot PCI completion timeout. BMG introduces the ability to have non-posted erase. Add driver support for non-posted erase with polling for erase completion. Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Reuven Abliyev <reuven.abliyev@intel.com> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com> Link: https://lore.kernel.org/r/20250617145159.3803852-9-alexander.usyskin@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
33 lines
736 B
C
33 lines
736 B
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright(c) 2019-2025, Intel Corporation. All rights reserved.
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*/
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#ifndef __INTEL_DG_NVM_AUX_H__
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#define __INTEL_DG_NVM_AUX_H__
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#include <linux/auxiliary_bus.h>
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#include <linux/container_of.h>
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#include <linux/ioport.h>
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#include <linux/types.h>
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#define INTEL_DG_NVM_REGIONS 13
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struct intel_dg_nvm_region {
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const char *name;
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};
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struct intel_dg_nvm_dev {
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struct auxiliary_device aux_dev;
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bool writable_override;
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bool non_posted_erase;
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struct resource bar;
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struct resource bar2;
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const struct intel_dg_nvm_region *regions;
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};
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#define auxiliary_dev_to_intel_dg_nvm_dev(auxiliary_dev) \
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container_of(auxiliary_dev, struct intel_dg_nvm_dev, aux_dev)
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#endif /* __INTEL_DG_NVM_AUX_H__ */
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