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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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b9e53f9ff4
Add plumbing to the AMD IOMMU driver to allow KVM to control whether or not an IRTE is configured to generate GA log interrupts. KVM only needs a notification if the target vCPU is blocking, so the vCPU can be awakened. If a vCPU is preempted or exits to userspace, KVM clears is_run, but will set the vCPU back to running when userspace does KVM_RUN and/or the vCPU task is scheduled back in, i.e. KVM doesn't need a notification. Unconditionally pass "true" in all KVM paths to isolate the IOMMU changes from the KVM changes insofar as possible. Opportunistically swap the ordering of parameters for amd_iommu_update_ga() so that the match amd_iommu_activate_guest_mode(). Note, as of this writing, the AMD IOMMU manual doesn't list GALogIntr as a non-cached field, but per AMD hardware architects, it's not cached and can be safely updated without an invalidation. Link: https://lore.kernel.org/all/b29b8c22-2fd4-4b5e-b755-9198874157c7@amd.com Cc: Vasant Hegde <vasant.hegde@amd.com> Cc: Joao Martins <joao.m.martins@oracle.com> Link: https://lore.kernel.org/r/20250611224604.313496-62-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
78 lines
1.9 KiB
C
78 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
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* Author: Joerg Roedel <joerg.roedel@amd.com>
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* Leo Duran <leo.duran@amd.com>
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*/
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#ifndef _ASM_X86_AMD_IOMMU_H
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#define _ASM_X86_AMD_IOMMU_H
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#include <linux/types.h>
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struct amd_iommu;
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#ifdef CONFIG_AMD_IOMMU
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struct task_struct;
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struct pci_dev;
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extern void amd_iommu_detect(void);
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#else /* CONFIG_AMD_IOMMU */
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static inline void amd_iommu_detect(void) { }
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#endif /* CONFIG_AMD_IOMMU */
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#if defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP)
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/* IOMMU AVIC Function */
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extern int amd_iommu_register_ga_log_notifier(int (*notifier)(u32));
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extern int amd_iommu_update_ga(void *data, int cpu, bool ga_log_intr);
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extern int amd_iommu_activate_guest_mode(void *data, int cpu, bool ga_log_intr);
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extern int amd_iommu_deactivate_guest_mode(void *data);
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#else /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */
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static inline int
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amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
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{
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return 0;
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}
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static inline int amd_iommu_update_ga(void *data, int cpu, bool ga_log_intr)
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{
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return 0;
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}
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static inline int amd_iommu_activate_guest_mode(void *data, int cpu, bool ga_log_intr)
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{
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return 0;
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}
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static inline int amd_iommu_deactivate_guest_mode(void *data)
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{
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return 0;
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}
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#endif /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */
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int amd_iommu_get_num_iommus(void);
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bool amd_iommu_pc_supported(void);
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u8 amd_iommu_pc_get_max_banks(unsigned int idx);
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u8 amd_iommu_pc_get_max_counters(unsigned int idx);
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int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn,
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u64 *value);
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int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn,
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u64 *value);
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struct amd_iommu *get_amd_iommu(unsigned int idx);
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#ifdef CONFIG_KVM_AMD_SEV
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int amd_iommu_snp_disable(void);
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#else
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static inline int amd_iommu_snp_disable(void) { return 0; }
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#endif
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#endif /* _ASM_X86_AMD_IOMMU_H */
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