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Add new helper macros and enums to help identifying the platform and some characteristics of it at runtime. Signed-off-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20250519-dev-axi-clkgen-limits-v6-4-bc4b3b61d1d4@analog.com Reviewed-by: David Lechner <dlechner@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
57 lines
1.6 KiB
C
57 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Analog Devices AXI common registers & definitions
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*
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* Copyright 2019 Analog Devices Inc.
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*
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* https://wiki.analog.com/resources/fpga/docs/axi_ip
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* https://wiki.analog.com/resources/fpga/docs/hdl/regmap
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*/
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#ifndef ADI_AXI_COMMON_H_
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#define ADI_AXI_COMMON_H_
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#define ADI_AXI_REG_VERSION 0x0000
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#define ADI_AXI_REG_FPGA_INFO 0x001C
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#define ADI_AXI_PCORE_VER(major, minor, patch) \
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(((major) << 16) | ((minor) << 8) | (patch))
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#define ADI_AXI_PCORE_VER_MAJOR(version) (((version) >> 16) & 0xff)
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#define ADI_AXI_PCORE_VER_MINOR(version) (((version) >> 8) & 0xff)
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#define ADI_AXI_PCORE_VER_PATCH(version) ((version) & 0xff)
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#define ADI_AXI_INFO_FPGA_TECH(info) (((info) >> 24) & 0xff)
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#define ADI_AXI_INFO_FPGA_FAMILY(info) (((info) >> 16) & 0xff)
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#define ADI_AXI_INFO_FPGA_SPEED_GRADE(info) (((info) >> 8) & 0xff)
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enum adi_axi_fpga_technology {
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ADI_AXI_FPGA_TECH_UNKNOWN = 0,
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ADI_AXI_FPGA_TECH_SERIES7,
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ADI_AXI_FPGA_TECH_ULTRASCALE,
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ADI_AXI_FPGA_TECH_ULTRASCALE_PLUS,
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};
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enum adi_axi_fpga_family {
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ADI_AXI_FPGA_FAMILY_UNKNOWN = 0,
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ADI_AXI_FPGA_FAMILY_ARTIX,
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ADI_AXI_FPGA_FAMILY_KINTEX,
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ADI_AXI_FPGA_FAMILY_VIRTEX,
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ADI_AXI_FPGA_FAMILY_ZYNQ,
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};
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enum adi_axi_fpga_speed_grade {
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ADI_AXI_FPGA_SPEED_UNKNOWN = 0,
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ADI_AXI_FPGA_SPEED_1 = 10,
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ADI_AXI_FPGA_SPEED_1L = 11,
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ADI_AXI_FPGA_SPEED_1H = 12,
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ADI_AXI_FPGA_SPEED_1HV = 13,
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ADI_AXI_FPGA_SPEED_1LV = 14,
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ADI_AXI_FPGA_SPEED_2 = 20,
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ADI_AXI_FPGA_SPEED_2L = 21,
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ADI_AXI_FPGA_SPEED_2LV = 22,
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ADI_AXI_FPGA_SPEED_3 = 30,
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};
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#endif /* ADI_AXI_COMMON_H_ */
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