mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-09-01 06:39:05 +00:00
61977ccf65
There is a PPU0 reset control bit in the same register as the PPU1
reset control. This missing reset control is for the PCK-600 unit
in the SoC. Manual tests show that the reset control indeed exists,
and if not configured, the system will hang when the PCK-600 registers
are accessed.
Add a reset entry for it at the end of the existing ones.
Fixes: 52dbf84857 ("dt-bindings: clk: sunxi-ng: document two Allwinner A523 CCUs")
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Link: https://patch.msgid.link/20250619171025.3359384-2-wens@kernel.org
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
27 lines
667 B
C
27 lines
667 B
C
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
|
|
/*
|
|
* Copyright (C) 2024 Arm Ltd.
|
|
*/
|
|
|
|
#ifndef _DT_BINDINGS_RST_SUN55I_A523_R_CCU_H_
|
|
#define _DT_BINDINGS_RST_SUN55I_A523_R_CCU_H_
|
|
|
|
#define RST_BUS_R_TIMER 0
|
|
#define RST_BUS_R_TWD 1
|
|
#define RST_BUS_R_PWMCTRL 2
|
|
#define RST_BUS_R_SPI 3
|
|
#define RST_BUS_R_SPINLOCK 4
|
|
#define RST_BUS_R_MSGBOX 5
|
|
#define RST_BUS_R_UART0 6
|
|
#define RST_BUS_R_UART1 7
|
|
#define RST_BUS_R_I2C0 8
|
|
#define RST_BUS_R_I2C1 9
|
|
#define RST_BUS_R_I2C2 10
|
|
#define RST_BUS_R_PPU1 11
|
|
#define RST_BUS_R_IR_RX 12
|
|
#define RST_BUS_R_RTC 13
|
|
#define RST_BUS_R_CPUCFG 14
|
|
#define RST_BUS_R_PPU0 15
|
|
|
|
#endif /* _DT_BINDINGS_RST_SUN55I_A523_R_CCU_H_ */
|