mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
synced 2025-08-29 02:27:36 +00:00
9d484eac1e
Id 173 was accidentially used two times for SRST_P_DDR_HWLP and
SRST_P_DDR_PHY. This makes both resets ambiguous and also causes build
warnings like:
drivers/clk/rockchip/rst-rk3562.c:21:57: error: initialized field overwritten [-Werror=override-init]
21 | #define RK3562_DDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000*4 + reg * 16 + bit)
| ^
drivers/clk/rockchip/rst-rk3562.c:266:9: note: in expansion of macro 'RK3562_DDRCRU_RESET_OFFSET'
266 | RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_PHY, 0, 8),
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/clk/rockchip/rst-rk3562.c:21:57: note: (near initialization for 'rk3562_register_offset[173]')
21 | #define RK3562_DDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000*4 + reg * 16 + bit)
| ^
drivers/clk/rockchip/rst-rk3562.c:266:9: note: in expansion of macro 'RK3562_DDRCRU_RESET_OFFSET'
266 | RK3562_DDRCRU_RESET_OFFSET(SRST_P_DDR_PHY, 0, 8),
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
To fix that issue give SRST_P_DDR_PHY a new and now unique id.
Reported-by: Stephen Boyd <sboyd@kernel.org>
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202503121743.0zcDf6nE-lkp@intel.com/
Fixes: dd113c4fef ("dt-bindings: clock: Add RK3562 cru")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250312215923.275625-1-heiko@sntech.de
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
359 lines
11 KiB
C
359 lines
11 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2024-2025 Rockchip Electronics Co. Ltd.
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*
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* Author: Elaine Zhang <zhangqing@rock-chips.com>
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*/
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#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3562_H
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#define _DT_BINDINGS_RESET_ROCKCHIP_RK3562_H
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/********Name=SOFTRST_CON01,Offset=0x404********/
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#define SRST_A_TOP_BIU 0
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#define SRST_A_TOP_VIO_BIU 1
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#define SRST_REF_PVTPLL_LOGIC 2
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/********Name=SOFTRST_CON03,Offset=0x40C********/
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#define SRST_NCOREPORESET0 3
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#define SRST_NCOREPORESET1 4
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#define SRST_NCOREPORESET2 5
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#define SRST_NCOREPORESET3 6
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#define SRST_NCORESET0 7
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#define SRST_NCORESET1 8
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#define SRST_NCORESET2 9
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#define SRST_NCORESET3 10
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#define SRST_NL2RESET 11
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/********Name=SOFTRST_CON04,Offset=0x410********/
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#define SRST_DAP 12
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#define SRST_P_DBG_DAPLITE 13
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#define SRST_REF_PVTPLL_CORE 14
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/********Name=SOFTRST_CON05,Offset=0x414********/
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#define SRST_A_CORE_BIU 15
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#define SRST_P_CORE_BIU 16
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#define SRST_H_CORE_BIU 17
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/********Name=SOFTRST_CON06,Offset=0x418********/
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#define SRST_A_NPU_BIU 18
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#define SRST_H_NPU_BIU 19
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#define SRST_A_RKNN 20
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#define SRST_H_RKNN 21
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#define SRST_REF_PVTPLL_NPU 22
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/********Name=SOFTRST_CON08,Offset=0x420********/
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#define SRST_A_GPU_BIU 23
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#define SRST_GPU 24
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#define SRST_REF_PVTPLL_GPU 25
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#define SRST_GPU_BRG_BIU 26
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/********Name=SOFTRST_CON09,Offset=0x424********/
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#define SRST_RKVENC_CORE 27
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#define SRST_A_VEPU_BIU 28
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#define SRST_H_VEPU_BIU 29
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#define SRST_A_RKVENC 30
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#define SRST_H_RKVENC 31
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/********Name=SOFTRST_CON10,Offset=0x428********/
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#define SRST_RKVDEC_HEVC_CA 32
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#define SRST_A_VDPU_BIU 33
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#define SRST_H_VDPU_BIU 34
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#define SRST_A_RKVDEC 35
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#define SRST_H_RKVDEC 36
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/********Name=SOFTRST_CON11,Offset=0x42C********/
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#define SRST_A_VI_BIU 37
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#define SRST_H_VI_BIU 38
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#define SRST_P_VI_BIU 39
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#define SRST_ISP 40
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#define SRST_A_VICAP 41
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#define SRST_H_VICAP 42
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#define SRST_D_VICAP 43
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#define SRST_I0_VICAP 44
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#define SRST_I1_VICAP 45
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#define SRST_I2_VICAP 46
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#define SRST_I3_VICAP 47
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/********Name=SOFTRST_CON12,Offset=0x430********/
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#define SRST_P_CSIHOST0 48
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#define SRST_P_CSIHOST1 49
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#define SRST_P_CSIHOST2 50
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#define SRST_P_CSIHOST3 51
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#define SRST_P_CSIPHY0 52
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#define SRST_P_CSIPHY1 53
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/********Name=SOFTRST_CON13,Offset=0x434********/
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#define SRST_A_VO_BIU 54
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#define SRST_H_VO_BIU 55
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#define SRST_A_VOP 56
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#define SRST_H_VOP 57
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#define SRST_D_VOP 58
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#define SRST_D_VOP1 59
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/********Name=SOFTRST_CON14,Offset=0x438********/
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#define SRST_A_RGA_BIU 60
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#define SRST_H_RGA_BIU 61
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#define SRST_A_RGA 62
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#define SRST_H_RGA 63
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#define SRST_RGA_CORE 64
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#define SRST_A_JDEC 65
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#define SRST_H_JDEC 66
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/********Name=SOFTRST_CON15,Offset=0x43C********/
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#define SRST_B_EBK_BIU 67
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#define SRST_P_EBK_BIU 68
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#define SRST_AHB2AXI_EBC 69
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#define SRST_H_EBC 70
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#define SRST_D_EBC 71
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#define SRST_H_EINK 72
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#define SRST_P_EINK 73
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/********Name=SOFTRST_CON16,Offset=0x440********/
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#define SRST_P_PHP_BIU 74
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#define SRST_A_PHP_BIU 75
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#define SRST_P_PCIE20 76
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#define SRST_PCIE20_POWERUP 77
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#define SRST_USB3OTG 78
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/********Name=SOFTRST_CON17,Offset=0x444********/
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#define SRST_PIPEPHY 79
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/********Name=SOFTRST_CON18,Offset=0x448********/
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#define SRST_A_BUS_BIU 80
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#define SRST_H_BUS_BIU 81
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#define SRST_P_BUS_BIU 82
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/********Name=SOFTRST_CON19,Offset=0x44C********/
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#define SRST_P_I2C1 83
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#define SRST_P_I2C2 84
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#define SRST_P_I2C3 85
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#define SRST_P_I2C4 86
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#define SRST_P_I2C5 87
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#define SRST_I2C1 88
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#define SRST_I2C2 89
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#define SRST_I2C3 90
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#define SRST_I2C4 91
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#define SRST_I2C5 92
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/********Name=SOFTRST_CON20,Offset=0x450********/
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#define SRST_BUS_GPIO3 93
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#define SRST_BUS_GPIO4 94
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/********Name=SOFTRST_CON21,Offset=0x454********/
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#define SRST_P_TIMER 95
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#define SRST_TIMER0 96
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#define SRST_TIMER1 97
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#define SRST_TIMER2 98
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#define SRST_TIMER3 99
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#define SRST_TIMER4 100
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#define SRST_TIMER5 101
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#define SRST_P_STIMER 102
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#define SRST_STIMER0 103
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#define SRST_STIMER1 104
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/********Name=SOFTRST_CON22,Offset=0x458********/
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#define SRST_P_WDTNS 105
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#define SRST_WDTNS 106
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#define SRST_P_GRF 107
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#define SRST_P_SGRF 108
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#define SRST_P_MAILBOX 109
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#define SRST_P_INTC 110
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#define SRST_A_BUS_GIC400 111
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#define SRST_A_BUS_GIC400_DEBUG 112
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/********Name=SOFTRST_CON23,Offset=0x45C********/
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#define SRST_A_BUS_SPINLOCK 113
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#define SRST_A_DCF 114
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#define SRST_P_DCF 115
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#define SRST_F_BUS_CM0_CORE 116
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#define SRST_T_BUS_CM0_JTAG 117
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#define SRST_H_ICACHE 118
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#define SRST_H_DCACHE 119
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/********Name=SOFTRST_CON24,Offset=0x460********/
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#define SRST_P_TSADC 120
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#define SRST_TSADC 121
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#define SRST_TSADCPHY 122
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#define SRST_P_DFT2APB 123
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/********Name=SOFTRST_CON25,Offset=0x464********/
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#define SRST_A_GMAC 124
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#define SRST_P_APB2ASB_VCCIO156 125
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#define SRST_P_DSIPHY 126
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#define SRST_P_DSITX 127
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#define SRST_P_CPU_EMA_DET 128
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#define SRST_P_HASH 129
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#define SRST_P_TOPCRU 130
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/********Name=SOFTRST_CON26,Offset=0x468********/
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#define SRST_P_ASB2APB_VCCIO156 131
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#define SRST_P_IOC_VCCIO156 132
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#define SRST_P_GPIO3_VCCIO156 133
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#define SRST_P_GPIO4_VCCIO156 134
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#define SRST_P_SARADC_VCCIO156 135
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#define SRST_SARADC_VCCIO156 136
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#define SRST_SARADC_VCCIO156_PHY 137
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/********Name=SOFTRST_CON27,Offset=0x46c********/
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#define SRST_A_MAC100 138
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/********Name=PMU0SOFTRST_CON00,Offset=0x10200********/
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#define SRST_P_PMU0_CRU 139
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#define SRST_P_PMU0_PMU 140
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#define SRST_PMU0_PMU 141
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#define SRST_P_PMU0_HP_TIMER 142
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#define SRST_PMU0_HP_TIMER 143
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#define SRST_PMU0_32K_HP_TIMER 144
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#define SRST_P_PMU0_PVTM 145
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#define SRST_PMU0_PVTM 146
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#define SRST_P_IOC_PMUIO 147
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#define SRST_P_PMU0_GPIO0 148
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#define SRST_PMU0_GPIO0 149
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#define SRST_P_PMU0_GRF 150
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#define SRST_P_PMU0_SGRF 151
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/********Name=PMU0SOFTRST_CON01,Offset=0x10204********/
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#define SRST_DDR_FAIL_SAFE 152
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#define SRST_P_PMU0_SCRKEYGEN 153
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/********Name=PMU0SOFTRST_CON02,Offset=0x10208********/
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#define SRST_P_PMU0_I2C0 154
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#define SRST_PMU0_I2C0 155
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/********Name=PMU1SOFTRST_CON00,Offset=0x18200********/
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#define SRST_P_PMU1_CRU 156
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#define SRST_H_PMU1_MEM 157
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#define SRST_H_PMU1_BIU 158
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#define SRST_P_PMU1_BIU 159
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#define SRST_P_PMU1_UART0 160
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#define SRST_S_PMU1_UART0 161
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/********Name=PMU1SOFTRST_CON01,Offset=0x18204********/
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#define SRST_P_PMU1_SPI0 162
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#define SRST_PMU1_SPI0 163
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#define SRST_P_PMU1_PWM0 164
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#define SRST_PMU1_PWM0 165
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/********Name=PMU1SOFTRST_CON02,Offset=0x18208********/
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#define SRST_F_PMU1_CM0_CORE 166
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#define SRST_T_PMU1_CM0_JTAG 167
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#define SRST_P_PMU1_WDTNS 168
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#define SRST_PMU1_WDTNS 169
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#define SRST_PMU1_MAILBOX 170
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/********Name=DDRSOFTRST_CON00,Offset=0x20200********/
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#define SRST_MSCH_BRG_BIU 171
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#define SRST_P_MSCH_BIU 172
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#define SRST_P_DDR_HWLP 173
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#define SRST_P_DDR_PHY 290
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#define SRST_P_DDR_DFICTL 174
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#define SRST_P_DDR_DMA2DDR 175
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/********Name=DDRSOFTRST_CON01,Offset=0x20204********/
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#define SRST_P_DDR_MON 176
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#define SRST_TM_DDR_MON 177
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#define SRST_P_DDR_GRF 178
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#define SRST_P_DDR_CRU 179
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#define SRST_P_SUBDDR_CRU 180
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/********Name=SUBDDRSOFTRST_CON00,Offset=0x28200********/
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#define SRST_MSCH_BIU 181
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#define SRST_DDR_PHY 182
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#define SRST_DDR_DFICTL 183
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#define SRST_DDR_SCRAMBLE 184
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#define SRST_DDR_MON 185
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#define SRST_A_DDR_SPLIT 186
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#define SRST_DDR_DMA2DDR 187
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/********Name=PERISOFTRST_CON01,Offset=0x30404********/
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#define SRST_A_PERI_BIU 188
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#define SRST_H_PERI_BIU 189
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#define SRST_P_PERI_BIU 190
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#define SRST_P_PERICRU 191
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/********Name=PERISOFTRST_CON02,Offset=0x30408********/
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#define SRST_H_SAI0_8CH 192
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#define SRST_M_SAI0_8CH 193
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#define SRST_H_SAI1_8CH 194
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#define SRST_M_SAI1_8CH 195
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#define SRST_H_SAI2_2CH 196
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#define SRST_M_SAI2_2CH 197
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/********Name=PERISOFTRST_CON03,Offset=0x3040C********/
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#define SRST_H_DSM 198
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#define SRST_DSM 199
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#define SRST_H_PDM 200
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#define SRST_M_PDM 201
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#define SRST_H_SPDIF 202
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#define SRST_M_SPDIF 203
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/********Name=PERISOFTRST_CON04,Offset=0x30410********/
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#define SRST_H_SDMMC0 204
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#define SRST_H_SDMMC1 205
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#define SRST_H_EMMC 206
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#define SRST_A_EMMC 207
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#define SRST_C_EMMC 208
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#define SRST_B_EMMC 209
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#define SRST_T_EMMC 210
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#define SRST_S_SFC 211
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#define SRST_H_SFC 212
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/********Name=PERISOFTRST_CON05,Offset=0x30414********/
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#define SRST_H_USB2HOST 213
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#define SRST_H_USB2HOST_ARB 214
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#define SRST_USB2HOST_UTMI 215
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/********Name=PERISOFTRST_CON06,Offset=0x30418********/
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#define SRST_P_SPI1 216
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#define SRST_SPI1 217
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#define SRST_P_SPI2 218
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#define SRST_SPI2 219
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/********Name=PERISOFTRST_CON07,Offset=0x3041C********/
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#define SRST_P_UART1 220
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#define SRST_P_UART2 221
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#define SRST_P_UART3 222
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#define SRST_P_UART4 223
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#define SRST_P_UART5 224
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#define SRST_P_UART6 225
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#define SRST_P_UART7 226
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#define SRST_P_UART8 227
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#define SRST_P_UART9 228
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#define SRST_S_UART1 229
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#define SRST_S_UART2 230
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/********Name=PERISOFTRST_CON08,Offset=0x30420********/
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#define SRST_S_UART3 231
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#define SRST_S_UART4 232
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#define SRST_S_UART5 233
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#define SRST_S_UART6 234
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#define SRST_S_UART7 235
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/********Name=PERISOFTRST_CON09,Offset=0x30424********/
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#define SRST_S_UART8 236
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#define SRST_S_UART9 237
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/********Name=PERISOFTRST_CON10,Offset=0x30428********/
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#define SRST_P_PWM1_PERI 238
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#define SRST_PWM1_PERI 239
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#define SRST_P_PWM2_PERI 240
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#define SRST_PWM2_PERI 241
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#define SRST_P_PWM3_PERI 242
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#define SRST_PWM3_PERI 243
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/********Name=PERISOFTRST_CON11,Offset=0x3042C********/
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#define SRST_P_CAN0 244
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#define SRST_CAN0 245
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#define SRST_P_CAN1 246
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#define SRST_CAN1 247
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/********Name=PERISOFTRST_CON12,Offset=0x30430********/
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#define SRST_A_CRYPTO 248
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#define SRST_H_CRYPTO 249
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#define SRST_P_CRYPTO 250
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#define SRST_CORE_CRYPTO 251
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#define SRST_PKA_CRYPTO 252
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#define SRST_H_KLAD 253
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#define SRST_P_KEY_READER 254
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#define SRST_H_RK_RNG_NS 255
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#define SRST_H_RK_RNG_S 256
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#define SRST_H_TRNG_NS 257
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#define SRST_H_TRNG_S 258
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#define SRST_H_CRYPTO_S 259
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/********Name=PERISOFTRST_CON13,Offset=0x30434********/
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#define SRST_P_PERI_WDT 260
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#define SRST_T_PERI_WDT 261
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#define SRST_A_SYSMEM 262
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#define SRST_H_BOOTROM 263
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#define SRST_P_PERI_GRF 264
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#define SRST_A_DMAC 265
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#define SRST_A_RKDMAC 267
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/********Name=PERISOFTRST_CON14,Offset=0x30438********/
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#define SRST_P_OTPC_NS 268
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#define SRST_SBPI_OTPC_NS 269
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#define SRST_USER_OTPC_NS 270
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#define SRST_P_OTPC_S 271
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#define SRST_SBPI_OTPC_S 272
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#define SRST_USER_OTPC_S 273
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#define SRST_OTPC_ARB 274
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#define SRST_P_OTPPHY 275
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#define SRST_OTP_NPOR 276
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/********Name=PERISOFTRST_CON15,Offset=0x3043C********/
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#define SRST_P_USB2PHY 277
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#define SRST_USB2PHY_POR 278
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#define SRST_USB2PHY_OTG 279
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#define SRST_USB2PHY_HOST 280
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#define SRST_P_PIPEPHY 281
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/********Name=PERISOFTRST_CON16,Offset=0x30440********/
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#define SRST_P_SARADC 282
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#define SRST_SARADC 283
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#define SRST_SARADC_PHY 284
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#define SRST_P_IOC_VCCIO234 285
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/********Name=PERISOFTRST_CON17,Offset=0x30444********/
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#define SRST_P_PERI_GPIO1 286
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#define SRST_P_PERI_GPIO2 287
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#define SRST_PERI_GPIO1 288
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#define SRST_PERI_GPIO2 289
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#endif
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