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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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3c2968fcd7
Introduces a reset controller driver for the Kendryte K230 SoC, resposible for managing the reset functionality of the CPUs and various sub-modules. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Link: https://lore.kernel.org/r/20250613-k230-reset-v4-1-e5266d2be440@pigmoral.tech Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
91 lines
2.0 KiB
C
91 lines
2.0 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (C) 2023-2024 Canaan Bright Sight Co., Ltd
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* Copyright (C) 2024-2025 Junhui Liu <junhui.liu@pigmoral.tech>
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*/
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#ifndef _DT_BINDINGS_CANAAN_K230_RST_H_
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#define _DT_BINDINGS_CANAAN_K230_RST_H_
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#define RST_CPU0 0
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#define RST_CPU1 1
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#define RST_CPU0_FLUSH 2
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#define RST_CPU1_FLUSH 3
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#define RST_AI 4
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#define RST_VPU 5
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#define RST_HISYS 6
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#define RST_HISYS_AHB 7
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#define RST_SDIO0 8
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#define RST_SDIO1 9
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#define RST_SDIO_AXI 10
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#define RST_USB0 11
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#define RST_USB1 12
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#define RST_USB0_AHB 13
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#define RST_USB1_AHB 14
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#define RST_SPI0 15
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#define RST_SPI1 16
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#define RST_SPI2 17
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#define RST_SEC 18
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#define RST_PDMA 19
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#define RST_SDMA 20
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#define RST_DECOMPRESS 21
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#define RST_SRAM 22
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#define RST_SHRM_AXIM 23
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#define RST_SHRM_AXIS 24
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#define RST_NONAI2D 25
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#define RST_MCTL 26
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#define RST_ISP 27
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#define RST_ISP_DW 28
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#define RST_DPU 29
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#define RST_DISP 30
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#define RST_GPU 31
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#define RST_AUDIO 32
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#define RST_TIMER0 33
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#define RST_TIMER1 34
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#define RST_TIMER2 35
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#define RST_TIMER3 36
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#define RST_TIMER4 37
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#define RST_TIMER5 38
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#define RST_TIMER_APB 39
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#define RST_HDI 40
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#define RST_WDT0 41
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#define RST_WDT1 42
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#define RST_WDT0_APB 43
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#define RST_WDT1_APB 44
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#define RST_TS_APB 45
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#define RST_MAILBOX 46
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#define RST_STC 47
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#define RST_PMU 48
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#define RST_LOSYS_APB 49
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#define RST_UART0 50
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#define RST_UART1 51
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#define RST_UART2 52
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#define RST_UART3 53
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#define RST_UART4 54
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#define RST_I2C0 55
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#define RST_I2C1 56
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#define RST_I2C2 57
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#define RST_I2C3 58
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#define RST_I2C4 59
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#define RST_JAMLINK0_APB 60
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#define RST_JAMLINK1_APB 61
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#define RST_JAMLINK2_APB 62
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#define RST_JAMLINK3_APB 63
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#define RST_CODEC_APB 64
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#define RST_GPIO_DB 65
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#define RST_GPIO_APB 66
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#define RST_ADC 67
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#define RST_ADC_APB 68
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#define RST_PWM_APB 69
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#define RST_SHRM_APB 70
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#define RST_CSI0 71
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#define RST_CSI1 72
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#define RST_CSI2 73
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#define RST_CSI_DPHY 74
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#define RST_ISP_AHB 75
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#define RST_M0 76
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#define RST_M1 77
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#define RST_M2 78
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#define RST_SPI2AXI 79
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#endif
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