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5c7fb203d0
Add documentation for the pin controller found on the Renesas RZ/G3E (R9A09G047) SoC. The RZ/G3E PFC is similar to the RZ/V2H SoC but has more pins(P00-PS3). Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241216195325.164212-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
42 lines
1.0 KiB
C
42 lines
1.0 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* This header provides constants for Renesas RZ/G3E family pinctrl bindings.
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*
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* Copyright (C) 2024 Renesas Electronics Corp.
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*
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*/
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#ifndef __DT_BINDINGS_PINCTRL_RENESAS_R9A09G047_PINCTRL_H__
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#define __DT_BINDINGS_PINCTRL_RENESAS_R9A09G047_PINCTRL_H__
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#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
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/* RZG3E_Px = Offset address of PFC_P_mn - 0x20 */
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#define RZG3E_P0 0
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#define RZG3E_P1 1
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#define RZG3E_P2 2
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#define RZG3E_P3 3
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#define RZG3E_P4 4
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#define RZG3E_P5 5
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#define RZG3E_P6 6
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#define RZG3E_P7 7
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#define RZG3E_P8 8
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#define RZG3E_PA 10
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#define RZG3E_PB 11
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#define RZG3E_PC 12
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#define RZG3E_PD 13
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#define RZG3E_PE 14
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#define RZG3E_PF 15
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#define RZG3E_PG 16
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#define RZG3E_PH 17
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#define RZG3E_PJ 19
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#define RZG3E_PK 20
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#define RZG3E_PL 21
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#define RZG3E_PM 22
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#define RZG3E_PS 28
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#define RZG3E_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZG3E_P##b, p, f)
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#define RZG3E_GPIO(port, pin) RZG2L_GPIO(RZG3E_P##port, pin)
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#endif /* __DT_BINDINGS_PINCTRL_RENESAS_R9A09G047_PINCTRL_H__ */
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