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https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
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7fa119f570
Add CMU_PERIS block compatible, and clock definitions. CMU_PERIS requires one bus clock dependency, and it's used for i.e the MCT. Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250104-exynos990-cmu-v1-1-9f54d69286d6@mentallysanemainliners.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
258 lines
8.9 KiB
C
258 lines
8.9 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (C) 2024 Igor Belwon <igor.belwon@mentallysanemainliners.org>
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*
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* Device Tree binding constants for Exynos990 clock controller.
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*/
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#ifndef _DT_BINDINGS_CLOCK_EXYNOS_990_H
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#define _DT_BINDINGS_CLOCK_EXYNOS_990_H
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/* CMU_TOP */
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#define CLK_FOUT_SHARED0_PLL 1
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#define CLK_FOUT_SHARED1_PLL 2
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#define CLK_FOUT_SHARED2_PLL 3
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#define CLK_FOUT_SHARED3_PLL 4
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#define CLK_FOUT_SHARED4_PLL 5
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#define CLK_FOUT_G3D_PLL 6
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#define CLK_FOUT_MMC_PLL 7
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#define CLK_MOUT_PLL_SHARED0 8
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#define CLK_MOUT_PLL_SHARED1 9
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#define CLK_MOUT_PLL_SHARED2 10
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#define CLK_MOUT_PLL_SHARED3 11
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#define CLK_MOUT_PLL_SHARED4 12
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#define CLK_MOUT_PLL_MMC 13
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#define CLK_MOUT_PLL_G3D 14
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#define CLK_MOUT_CMU_APM_BUS 15
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#define CLK_MOUT_CMU_AUD_CPU 16
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#define CLK_MOUT_CMU_BUS0_BUS 17
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#define CLK_MOUT_CMU_BUS1_BUS 18
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#define CLK_MOUT_CMU_BUS1_SSS 19
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#define CLK_MOUT_CMU_CIS_CLK0 20
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#define CLK_MOUT_CMU_CIS_CLK1 21
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#define CLK_MOUT_CMU_CIS_CLK2 22
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#define CLK_MOUT_CMU_CIS_CLK3 23
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#define CLK_MOUT_CMU_CIS_CLK4 24
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#define CLK_MOUT_CMU_CIS_CLK5 25
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#define CLK_MOUT_CMU_CMU_BOOST 26
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#define CLK_MOUT_CMU_CORE_BUS 27
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#define CLK_MOUT_CMU_CPUCL0_DBG_BUS 28
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#define CLK_MOUT_CMU_CPUCL0_SWITCH 29
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#define CLK_MOUT_CMU_CPUCL1_SWITCH 30
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#define CLK_MOUT_CMU_CPUCL2_BUSP 31
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#define CLK_MOUT_CMU_CPUCL2_SWITCH 32
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#define CLK_MOUT_CMU_CSIS_BUS 33
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#define CLK_MOUT_CMU_CSIS_OIS_MCU 34
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#define CLK_MOUT_CMU_DNC_BUS 35
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#define CLK_MOUT_CMU_DNC_BUSM 36
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#define CLK_MOUT_CMU_DNS_BUS 37
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#define CLK_MOUT_CMU_DPU 38
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#define CLK_MOUT_CMU_DPU_ALT 39
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#define CLK_MOUT_CMU_DSP_BUS 40
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#define CLK_MOUT_CMU_G2D_G2D 41
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#define CLK_MOUT_CMU_G2D_MSCL 42
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#define CLK_MOUT_CMU_HPM 43
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#define CLK_MOUT_CMU_HSI0_BUS 44
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#define CLK_MOUT_CMU_HSI0_DPGTC 45
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#define CLK_MOUT_CMU_HSI0_USB31DRD 46
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#define CLK_MOUT_CMU_HSI0_USBDP_DEBUG 47
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#define CLK_MOUT_CMU_HSI1_BUS 48
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#define CLK_MOUT_CMU_HSI1_MMC_CARD 49
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#define CLK_MOUT_CMU_HSI1_PCIE 50
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#define CLK_MOUT_CMU_HSI1_UFS_CARD 51
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#define CLK_MOUT_CMU_HSI1_UFS_EMBD 52
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#define CLK_MOUT_CMU_HSI2_BUS 53
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#define CLK_MOUT_CMU_HSI2_PCIE 54
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#define CLK_MOUT_CMU_IPP_BUS 55
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#define CLK_MOUT_CMU_ITP_BUS 56
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#define CLK_MOUT_CMU_MCSC_BUS 57
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#define CLK_MOUT_CMU_MCSC_GDC 58
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#define CLK_MOUT_CMU_CMU_BOOST_CPU 59
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#define CLK_MOUT_CMU_MFC0_MFC0 60
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#define CLK_MOUT_CMU_MFC0_WFD 61
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#define CLK_MOUT_CMU_MIF_BUSP 62
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#define CLK_MOUT_CMU_MIF_SWITCH 63
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#define CLK_MOUT_CMU_NPU_BUS 64
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#define CLK_MOUT_CMU_PERIC0_BUS 65
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#define CLK_MOUT_CMU_PERIC0_IP 66
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#define CLK_MOUT_CMU_PERIC1_BUS 67
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#define CLK_MOUT_CMU_PERIC1_IP 68
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#define CLK_MOUT_CMU_PERIS_BUS 69
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#define CLK_MOUT_CMU_SSP_BUS 70
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#define CLK_MOUT_CMU_TNR_BUS 71
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#define CLK_MOUT_CMU_VRA_BUS 72
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#define CLK_DOUT_CMU_APM_BUS 73
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#define CLK_DOUT_CMU_AUD_CPU 74
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#define CLK_DOUT_CMU_BUS0_BUS 75
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#define CLK_DOUT_CMU_BUS1_BUS 76
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#define CLK_DOUT_CMU_BUS1_SSS 77
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#define CLK_DOUT_CMU_CIS_CLK0 78
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#define CLK_DOUT_CMU_CIS_CLK1 79
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#define CLK_DOUT_CMU_CIS_CLK2 80
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#define CLK_DOUT_CMU_CIS_CLK3 81
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#define CLK_DOUT_CMU_CIS_CLK4 82
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#define CLK_DOUT_CMU_CIS_CLK5 83
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#define CLK_DOUT_CMU_CMU_BOOST 84
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#define CLK_DOUT_CMU_CORE_BUS 85
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#define CLK_DOUT_CMU_CPUCL0_DBG_BUS 86
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#define CLK_DOUT_CMU_CPUCL0_SWITCH 87
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#define CLK_DOUT_CMU_CPUCL1_SWITCH 88
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#define CLK_DOUT_CMU_CPUCL2_BUSP 89
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#define CLK_DOUT_CMU_CPUCL2_SWITCH 90
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#define CLK_DOUT_CMU_CSIS_BUS 91
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#define CLK_DOUT_CMU_CSIS_OIS_MCU 92
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#define CLK_DOUT_CMU_DNC_BUS 93
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#define CLK_DOUT_CMU_DNC_BUSM 94
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#define CLK_DOUT_CMU_DNS_BUS 95
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#define CLK_DOUT_CMU_DSP_BUS 96
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#define CLK_DOUT_CMU_G2D_G2D 97
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#define CLK_DOUT_CMU_G2D_MSCL 98
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#define CLK_DOUT_CMU_G3D_SWITCH 99
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#define CLK_DOUT_CMU_HPM 100
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#define CLK_DOUT_CMU_HSI0_BUS 101
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#define CLK_DOUT_CMU_HSI0_DPGTC 102
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#define CLK_DOUT_CMU_HSI0_USB31DRD 103
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#define CLK_DOUT_CMU_HSI0_USBDP_DEBUG 104
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#define CLK_DOUT_CMU_HSI1_BUS 105
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#define CLK_DOUT_CMU_HSI1_MMC_CARD 106
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#define CLK_DOUT_CMU_HSI1_PCIE 107
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#define CLK_DOUT_CMU_HSI1_UFS_CARD 108
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#define CLK_DOUT_CMU_HSI1_UFS_EMBD 109
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#define CLK_DOUT_CMU_HSI2_BUS 110
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#define CLK_DOUT_CMU_HSI2_PCIE 111
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#define CLK_DOUT_CMU_IPP_BUS 112
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#define CLK_DOUT_CMU_ITP_BUS 113
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#define CLK_DOUT_CMU_MCSC_BUS 114
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#define CLK_DOUT_CMU_MCSC_GDC 115
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#define CLK_DOUT_CMU_CMU_BOOST_CPU 116
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#define CLK_DOUT_CMU_MFC0_MFC0 117
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#define CLK_DOUT_CMU_MFC0_WFD 118
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#define CLK_DOUT_CMU_MIF_BUSP 119
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#define CLK_DOUT_CMU_NPU_BUS 120
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#define CLK_DOUT_CMU_OTP 121
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#define CLK_DOUT_CMU_PERIC0_BUS 122
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#define CLK_DOUT_CMU_PERIC0_IP 123
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#define CLK_DOUT_CMU_PERIC1_BUS 124
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#define CLK_DOUT_CMU_PERIC1_IP 125
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#define CLK_DOUT_CMU_PERIS_BUS 126
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#define CLK_DOUT_CMU_SSP_BUS 127
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#define CLK_DOUT_CMU_TNR_BUS 128
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#define CLK_DOUT_CMU_VRA_BUS 129
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#define CLK_DOUT_CMU_DPU 130
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#define CLK_DOUT_CMU_DPU_ALT 131
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#define CLK_DOUT_CMU_SHARED0_DIV2 132
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#define CLK_DOUT_CMU_SHARED0_DIV3 133
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#define CLK_DOUT_CMU_SHARED0_DIV4 134
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#define CLK_DOUT_CMU_SHARED1_DIV2 135
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#define CLK_DOUT_CMU_SHARED1_DIV3 136
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#define CLK_DOUT_CMU_SHARED1_DIV4 137
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#define CLK_DOUT_CMU_SHARED2_DIV2 138
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#define CLK_DOUT_CMU_SHARED4_DIV2 139
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#define CLK_DOUT_CMU_SHARED4_DIV3 140
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#define CLK_DOUT_CMU_SHARED4_DIV4 141
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#define CLK_GOUT_CMU_G3D_BUS 142
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#define CLK_GOUT_CMU_MIF_SWITCH 143
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#define CLK_GOUT_CMU_APM_BUS 144
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#define CLK_GOUT_CMU_AUD_CPU 145
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#define CLK_GOUT_CMU_BUS0_BUS 146
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#define CLK_GOUT_CMU_BUS1_BUS 147
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#define CLK_GOUT_CMU_BUS1_SSS 148
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#define CLK_GOUT_CMU_CIS_CLK0 149
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#define CLK_GOUT_CMU_CIS_CLK1 150
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#define CLK_GOUT_CMU_CIS_CLK2 151
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#define CLK_GOUT_CMU_CIS_CLK3 152
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#define CLK_GOUT_CMU_CIS_CLK4 153
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#define CLK_GOUT_CMU_CIS_CLK5 154
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#define CLK_GOUT_CMU_CORE_BUS 155
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#define CLK_GOUT_CMU_CPUCL0_DBG_BUS 156
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#define CLK_GOUT_CMU_CPUCL0_SWITCH 157
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#define CLK_GOUT_CMU_CPUCL1_SWITCH 158
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#define CLK_GOUT_CMU_CPUCL2_BUSP 159
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#define CLK_GOUT_CMU_CPUCL2_SWITCH 160
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#define CLK_GOUT_CMU_CSIS_BUS 161
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#define CLK_GOUT_CMU_CSIS_OIS_MCU 162
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#define CLK_GOUT_CMU_DNC_BUS 163
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#define CLK_GOUT_CMU_DNC_BUSM 164
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#define CLK_GOUT_CMU_DNS_BUS 165
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#define CLK_GOUT_CMU_DPU 166
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#define CLK_GOUT_CMU_DPU_BUS 167
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#define CLK_GOUT_CMU_DSP_BUS 168
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#define CLK_GOUT_CMU_G2D_G2D 169
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#define CLK_GOUT_CMU_G2D_MSCL 170
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#define CLK_GOUT_CMU_G3D_SWITCH 171
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#define CLK_GOUT_CMU_HPM 172
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#define CLK_GOUT_CMU_HSI0_BUS 173
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#define CLK_GOUT_CMU_HSI0_DPGTC 174
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#define CLK_GOUT_CMU_HSI0_USB31DRD 175
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#define CLK_GOUT_CMU_HSI0_USBDP_DEBUG 176
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#define CLK_GOUT_CMU_HSI1_BUS 177
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#define CLK_GOUT_CMU_HSI1_MMC_CARD 178
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#define CLK_GOUT_CMU_HSI1_PCIE 179
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#define CLK_GOUT_CMU_HSI1_UFS_CARD 180
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#define CLK_GOUT_CMU_HSI1_UFS_EMBD 181
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#define CLK_GOUT_CMU_HSI2_BUS 182
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#define CLK_GOUT_CMU_HSI2_PCIE 183
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#define CLK_GOUT_CMU_IPP_BUS 184
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#define CLK_GOUT_CMU_ITP_BUS 185
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#define CLK_GOUT_CMU_MCSC_BUS 186
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#define CLK_GOUT_CMU_MCSC_GDC 187
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#define CLK_GOUT_CMU_MFC0_MFC0 188
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#define CLK_GOUT_CMU_MFC0_WFD 189
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#define CLK_GOUT_CMU_MIF_BUSP 190
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#define CLK_GOUT_CMU_NPU_BUS 191
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#define CLK_GOUT_CMU_PERIC0_BUS 192
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#define CLK_GOUT_CMU_PERIC0_IP 193
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#define CLK_GOUT_CMU_PERIC1_BUS 194
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#define CLK_GOUT_CMU_PERIC1_IP 195
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#define CLK_GOUT_CMU_PERIS_BUS 196
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#define CLK_GOUT_CMU_SSP_BUS 197
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#define CLK_GOUT_CMU_TNR_BUS 198
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#define CLK_GOUT_CMU_VRA_BUS 199
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/* CMU_HSI0 */
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#define CLK_MOUT_HSI0_BUS_USER 1
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#define CLK_MOUT_HSI0_USB31DRD_USER 2
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#define CLK_MOUT_HSI0_USBDP_DEBUG_USER 3
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#define CLK_MOUT_HSI0_DPGTC_USER 4
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#define CLK_GOUT_HSI0_DP_LINK_DP_GTC_CLK 5
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#define CLK_GOUT_HSI0_DP_LINK_PCLK 6
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#define CLK_GOUT_HSI0_D_TZPC_HSI0_PCLK 7
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#define CLK_GOUT_HSI0_LHM_AXI_P_HSI0_CLK 8
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#define CLK_GOUT_HSI0_PPMU_HSI0_BUS1_ACLK 9
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#define CLK_GOUT_HSI0_PPMU_HSI0_BUS1_PCLK 10
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#define CLK_GOUT_HSI0_CLK_HSI0_BUS_CLK 11
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#define CLK_GOUT_HSI0_SYSMMU_USB_CLK_S2 12
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#define CLK_GOUT_HSI0_SYSREG_HSI0_PCLK 13
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#define CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL 14
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#define CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY 15
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#define CLK_GOUT_HSI0_USB31DRD_USB31DRD_REF_CLK_40 16
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#define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_REF_SOC_PLL 17
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#define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_SCL_APB 18
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#define CLK_GOUT_HSI0_USB31DRD_USBPCS_APB_CLK 19
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#define CLK_GOUT_HSI0_VGEN_LITE_HSI0_CLK 20
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#define CLK_GOUT_HSI0_CMU_HSI0_PCLK 21
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#define CLK_GOUT_HSI0_XIU_D_HSI0_ACLK 22
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/* CMU_PERIS */
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#define CLK_MOUT_PERIS_BUS_USER 1
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#define CLK_MOUT_PERIS_CLK_PERIS_GIC 2
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#define CLK_GOUT_PERIS_SYSREG_PERIS_PCLK 3
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#define CLK_GOUT_PERIS_WDT_CLUSTER2_PCLK 4
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#define CLK_GOUT_PERIS_WDT_CLUSTER0_PCLK 5
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#define CLK_CLK_PERIS_PERIS_CMU_PERIS_PCLK 6
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#define CLK_GOUT_PERIS_CLK_PERIS_BUSP_CLK 7
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#define CLK_GOUT_PERIS_CLK_PERIS_OSCCLK_CLK 8
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#define CLK_GOUT_PERIS_CLK_PERIS_GIC_CLK 9
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#define CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKM 10
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#define CLK_GOUT_PERIS_OTP_CON_BIRA_PCLK 11
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#define CLK_GOUT_PERIS_GIC_CLK 12
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#define CLK_GOUT_PERIS_LHM_AXI_P_PERIS_CLK 13
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#define CLK_GOUT_PERIS_MCT_PCLK 14
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#define CLK_GOUT_PERIS_OTP_CON_TOP_PCLK 15
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#define CLK_GOUT_PERIS_D_TZPC_PERIS_PCLK 16
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#define CLK_GOUT_PERIS_TMU_TOP_PCLK 17
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#define CLK_GOUT_PERIS_OTP_CON_BIRA_OSCCLK 18
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#define CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK 19
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#endif
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